公开(公告)号：US20250048622A1

公开(公告)日：2025-02-06

申请号：US18601447

申请日：2024-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Geun CHOI ,  Kyung Hwan KIM ,  Joong Chan SHIN

IPC: H10B12/00

Abstract: A semiconductor memory device may include includes a bit line and a back gate strap line extending on a substrate, an active pattern on the bit line and the back gate strap line, a word line on a first side wall of the active pattern, a back gate electrode on a second side wall of the active pattern and connected to the back gate strap line, a data storage pattern connected to a face of the active pattern, and a word line contact plug connected to the word line. A first face of the back gate electrode and a first face of the word line may face the bit line and the back gate strap line. The first face of the back gate electrode may be connected to the back gate strap line. A second face of the word line may be connected to the word line contact plug.

公开(公告)号：US20180158718A1

公开(公告)日：2018-06-07

申请号：US15667118

申请日：2017-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONG RYUL LEE ,  Joong Chan SHIN ,  Dong Jun LEE ,  Ho Ouk LEE ,  Ji Min CHOI ,  Ji Young KIM ,  Chan Sic YOON ,  Chang Hyun CHO

IPC: H01L21/764 ,  H01L21/768 ,  H01L29/06 ,  H01L29/49 ,  H01L23/522

CPC classification number: H01L21/764 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/522 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L29/0649 ,  H01L29/4983

Abstract: A method for fabricating a semiconductor device includes providing a substrate including a cell region including a bit line structure, a bit line spacer and a lower electrode and a peripheral circuit region including first to third impurity regions, forming an interlayer insulating film on the peripheral circuit region, forming a first metal layer on the interlayer insulating film, forming a first trench and a second trench in the first metal layer between the first and second impurity regions, the second trench is disposed between the second and third impurity regions and exposes the interlayer insulating film, forming a first capping pattern on the first trench to form an air gap in the first trench, filling the second trench with a first insulating material, and forming, on the first metal layer, a contact connected to the third impurity region.