公开(公告)号：US11669773B2

公开(公告)日：2023-06-06

申请号：US16915786

申请日：2020-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungju Kim ,  Hyojin Choi ,  In Huh ,  Jeonghoon Ko ,  Changwook Jeong ,  Younsik Park ,  Joonwan Chai

IPC: G06N20/00 ,  G06F9/30 ,  G06F9/38 ,  G06F30/3308 ,  G06F18/214

CPC classification number: G06N20/00 ,  G06F9/30036 ,  G06F9/3879 ,  G06F18/214 ,  G06F30/3308

Abstract: An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.

公开(公告)号：US20210117193A1

公开(公告)日：2021-04-22

申请号：US16915786

申请日：2020-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungju Kim ,  Hyojin Choi ,  In Huh ,  Jeonghoon Ko ,  Changwook Jeong ,  Younsik Park ,  Joonwan Chai

IPC: G06F9/30 ,  G06N20/00 ,  G06F9/38 ,  G06K9/62

Abstract: An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.