公开(公告)号：US11532336B2

公开(公告)日：2022-12-20

申请号：US17340423

申请日：2021-06-07

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hyojin Choi ,  Jaewon Ko ,  Hyeongtae Kim ,  Younsik Park ,  Hyeonsik Son

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C11/408 ,  G11C29/00

摘要： A memory device including: a memory cell array including a plurality of memory cell rows; an address buffer configured to store addresses of target rows of the plurality of memory cell rows, wherein the addresses of the target rows have been repeatedly accessed; a minimum access output circuit configured to select, when there are a plurality of rows having a same minimum access count among the target rows, any one of the plurality of rows having the same minimum access count as a minimum access row based on a selection command value, and to output an index value of the minimum access row; and a control circuit configured to output a command instructing replacement of an address corresponding to the index value of the minimum access row with an address of an access row and storage of the address of the access row in the address buffer.

公开(公告)号：US11669773B2

公开(公告)日：2023-06-06

申请号：US16915786

申请日：2020-06-29

申请人： Samsung Electronics Co., Ltd.

发明人： Seungju Kim ,  Hyojin Choi ,  In Huh ,  Jeonghoon Ko ,  Changwook Jeong ,  Younsik Park ,  Joonwan Chai

IPC分类号： G06N20/00 ,  G06F9/30 ,  G06F9/38 ,  G06F30/3308 ,  G06F18/214

CPC分类号： G06N20/00 ,  G06F9/30036 ,  G06F9/3879 ,  G06F18/214 ,  G06F30/3308

摘要： An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.

公开(公告)号：US20210117193A1

公开(公告)日：2021-04-22

申请号：US16915786

申请日：2020-06-29

申请人： Samsung Electronics Co., Ltd.

发明人： Seungju Kim ,  Hyojin Choi ,  In Huh ,  Jeonghoon Ko ,  Changwook Jeong ,  Younsik Park ,  Joonwan Chai

IPC分类号： G06F9/30 ,  G06N20/00 ,  G06F9/38 ,  G06K9/62

摘要： An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.