Method for detecting defects in semiconductor device

    公开(公告)号:US11507801B2

    公开(公告)日:2022-11-22

    申请号:US16505155

    申请日:2019-07-08

    IPC分类号: G06N3/04 G06N3/08 G06F30/30

    摘要: A method for detecting defects in a semiconductor device includes pre-training a pre-trained convolutional neural network (CNN) model using a sampled clean data set extracted from a first data set; training a normal convolutional neural network model and a label-noise convolutional neural network model using first data of the first data set and the pre-trained convolutional neural network model. The method also includes outputting a first prediction result on whether second data of a second data set is good or bad using the second data and the normal convolutional neural network model; and outputting a second prediction result on whether second data is good or bad using the second data and the label-noise convolutional neural network model. The first prediction result is compared with the second prediction result to perform noise correction when there is a label difference. Third data created as results of the noise correction is added to the sampled clean data set. The normal convolutional neural network model and the label-noise convolutional neural network model are additionally using the sampled clean data set with the third data added.

    METHOD AND APPARATUS FOR SELECTING MODEL OF MACHINE LEARNING BASED ON META-LEARNING

    公开(公告)号:US20200042896A1

    公开(公告)日:2020-02-06

    申请号:US16518104

    申请日:2019-07-22

    摘要: A method of selecting a model of machine learning executed by a processor is provided. The method includes: receiving at least one data-set; configuring a configuration space for machine learning of the at least one data-set; extracting, from the at least one data-set, a meta-feature including quantitative information about the data-set; calculating performance of the machine learning for the at least one data-set based on a plurality of configurations included in the configuration space; executing meta-learning based on the meta-feature, the plurality of configurations, and the calculated performance; and optimizing the configuration space based on a result of executing the meta-learning.

    Simulation system for semiconductor process and simulation method thereof

    公开(公告)号:US11574095B2

    公开(公告)日:2023-02-07

    申请号:US16906038

    申请日:2020-06-19

    摘要: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

    ELECTRONIC DEVICES GENERATING VERIFICATION VECTOR FOR VERIFYING SEMICONDUCTOR CIRCUIT AND METHODS OF OPERATING THE SAME

    公开(公告)号:US20210117193A1

    公开(公告)日:2021-04-22

    申请号:US16915786

    申请日:2020-06-29

    摘要: An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.