利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

7 条记录 (耗时 0.034 秒)

    Semiconductor memory device with operation functions to be used during a modified read or write mode
    2.
    发明授权
    Semiconductor memory device with operation functions to be used during a modified read or write mode 有权
    具有操作功能的半导体存储器件在修改的读取/写入模式期间被使用

    公开(公告)号：US09292425B2

    公开(公告)日：2016-03-22

    申请号：US13966585

    申请日：2013-08-14

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Hyojin Choi ,  Chulwoo Park ,  Uksong Kang ,  Haksoo Yu

    IPC分类号： G06F12/00 ,  G11C7/10 ,  G11C11/4076

    CPC分类号： G06F12/00 ,  G11C7/1006 ,  G11C11/4076

    摘要： A semiconductor memory device performs a modified read operation or a modified write operation. The semiconductor memory device includes a memory cell array, a read circuit, and a write circuit. The semiconductor memory device further includes an operation unit performing an operation on read data obtained by the read circuit according to operation assignment information applied through an address line to reduce memory access time when entering a modified read mode. In addition, the semiconductor memory device may optionally manage a normal read mode and the modified read mode and allow operation result data output from the operation unit to be written by the write circuit in the modified read mode.

    摘要翻译： 半导体存储器件执行修改的读取操作或修改的写入操作。 半导体存储器件包括存储单元阵列，读取电路和写入电路。 半导体存储器件还包括操作单元，根据通过地址线施加的操作分配信息，对由读取电路获得的读取数据执行操作，以减少进入修改的读取模式时的存储器访问时间。 此外，半导体存储器件可以可选地管理正常读取模式和修改读取模式，并且允许由操作单元输出的操作结果数据由修改读取模式下的写入电路写入。

    ELECTRONIC DEVICES GENERATING VERIFICATION VECTOR FOR VERIFYING SEMICONDUCTOR CIRCUIT AND METHODS OF OPERATING THE SAME
    3.
    发明申请
    ELECTRONIC DEVICES GENERATING VERIFICATION VECTOR FOR VERIFYING SEMICONDUCTOR CIRCUIT AND METHODS OF OPERATING THE SAME 有权

    公开(公告)号：US20210117193A1

    公开(公告)日：2021-04-22

    申请号：US16915786

    申请日：2020-06-29

    申请人： Samsung Electronics Co., Ltd.

    发明人： Seungju Kim ,  Hyojin Choi ,  In Huh ,  Jeonghoon Ko ,  Changwook Jeong ,  Younsik Park ,  Joonwan Chai

    IPC分类号： G06F9/30 ,  G06N20/00 ,  G06F9/38 ,  G06K9/62

    摘要： An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.

    Memory device for processing a row-hammer refresh operation and a method of operating thereof
    6.
    发明授权
    Memory device for processing a row-hammer refresh operation and a method of operating thereof 有权

    公开(公告)号：US11532336B2

    公开(公告)日：2022-12-20

    申请号：US17340423

    申请日：2021-06-07

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Hyojin Choi ,  Jaewon Ko ,  Hyeongtae Kim ,  Younsik Park ,  Hyeonsik Son

    IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C11/408 ,  G11C29/00

    摘要： A memory device including: a memory cell array including a plurality of memory cell rows; an address buffer configured to store addresses of target rows of the plurality of memory cell rows, wherein the addresses of the target rows have been repeatedly accessed; a minimum access output circuit configured to select, when there are a plurality of rows having a same minimum access count among the target rows, any one of the plurality of rows having the same minimum access count as a minimum access row based on a selection command value, and to output an index value of the minimum access row; and a control circuit configured to output a command instructing replacement of an address corresponding to the index value of the minimum access row with an address of an access row and storage of the address of the access row in the address buffer.