公开(公告)号：US20240114704A1

公开(公告)日：2024-04-04

申请号：US18187803

申请日：2023-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyoung KWON ,  Jiyoung KIM ,  Woosung YANG ,  Sukkang SUNG

IPC: H10B80/00 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B80/00 ,  H10B43/27 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device may include a first substrate, a peripheral circuit structure on the first substrate, the peripheral circuit structure including first bonding pads in an upper portion of the peripheral circuit structure, and a cell array structure on the peripheral circuit structure. The cell array structure may include a second substrate, a stack interposed between the peripheral circuit structure and the second substrate, a first insulating layer enclosing the stack, a dummy plug penetrating the first insulating layer, a second insulating layer on the dummy plug, and second bonding pads interposed between the stack and the peripheral circuit structure and connected to the dummy plug. The first bonding pads may contact the second bonding pads, and the dummy plug may be electrically connected to the first bonding pads and the second bonding pads. A top surface of the dummy plug may contact the second insulating layer.

公开(公告)号：US20240405091A1

公开(公告)日：2024-12-05

申请号：US18541229

申请日：2023-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNHYOUNG KIM ,  Joonyoung KWON ,  Jiyoung KIM ,  Sukkang SUNG

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor device includes a gate stacking structure including alternating gate electrodes and insulation layers on an insulation portion, a channel structure crossing the insulation portion and extending through the gate stacking structure, and a horizontal conductive layer connected to the channel structure between the insulation portion and the gate stacking structure, the horizontal conductive layer including a doped monocrystalline semiconductor layer having a dopant.

公开(公告)号：US20240178168A1

公开(公告)日：2024-05-30

申请号：US18237962

申请日：2023-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho KIM ,  Woosung YANG ,  Joonyoung KWON ,  Jiyoung KIM ,  Sukkang SUNG

IPC: H01L23/00 ,  H10B41/50 ,  H10B43/50

CPC classification number: H01L24/08 ,  H10B41/50 ,  H10B43/50 ,  H01L2224/08145

Abstract: A semiconductor device includes a first substrate structure including a substrate, circuit elements on the substrate, a first interconnection structure on the circuit elements, and first metal bonding layers on the first interconnection structure; and a second substrate structure connected to the first substrate structure, and the second substrate structure includes: a plating layer; gate electrodes stacked and spaced apart from each other in a first direction below the plating layer; channel structures penetrating through the gate electrodes and extending in the first direction; a separation region penetrating through the gate electrodes and extending in a second direction; a second interconnection structure below the gate electrodes and the channel structures; second metal bonding layers below the second interconnection structure and connected to the first metal bonding layers; and dummy pattern layers between the second metal bonding layers, extending in the second direction, and including an insulating material.