公开(公告)号：US20230017908A1

公开(公告)日：2023-01-19

申请号：US17708470

申请日：2022-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyoung OH

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/538 ,  H01L23/522 ,  H01L23/48

Abstract: A semiconductor package includes: a substrate structure having a first surface and an opposite second surface; a semiconductor chip on the first surface; and a connection bump on the second surface. The substrate structure includes: interconnection patterns disposed at different levels relative to the second surface; connection vias connecting the interconnection patterns; and a passivation layer covering a portion of the interconnection patterns and having an opening. The interconnection patterns include a first pattern and a second pattern, wherein the first pattern and the second pattern are adjacent to the second surface, and wherein a side surface of the first pattern faces a side surface of the second pattern. The second pattern includes a pad pattern and a metal layer in contact with the pad pattern and the connection bump. The first pattern has a first thickness and the second pattern has a pad thickness that is greater than the first thickness.

公开(公告)号：US20250140726A1

公开(公告)日：2025-05-01

申请号：US18738153

申请日：2024-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunglyul LEE ,  Jooyoung OH

IPC: H01L23/00

Abstract: A semiconductor package includes: a package substrate having a first region and a second region; first connection pads disposed on the first region of the package substrate, and having a first height; second connection pads disposed on the second region of the package substrate, and having a second height that is lower than the first height; a semiconductor chip including first chip pads, second chip pads, and a protective insulating layer, wherein the first chip pads are disposed in the first region, wherein the second chip pads are disposed in the second region, and wherein the protective insulating layer is disposed on the second chip pads; first bump structures disposed on the first chip pads, and respectively connected to the first connection pads; and second bump structures disposed on the protective insulating layer, wherein the second bump structures are respectively connected to the second connection pads.

公开(公告)号：US20250054896A1

公开(公告)日：2025-02-13

申请号：US18779409

申请日：2024-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyoung OH

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a package substrate including upper pads disposed at an upper portion of the package substrate, a solder resist layer disposed on the package substrate, the solder resist layer having a plurality of openings exposing the upper pads, a first adhesive layer disposed in at least a portion of an opening of the plurality of openings, a semiconductor chip disposed on the first adhesive layer, a second adhesive layer disposed between the first adhesive layer and the semiconductor chip, and a conductive member electrically connecting at least one of the upper pads and the semiconductor chip to each other.

公开(公告)号：US20220208729A1

公开(公告)日：2022-06-30

申请号：US17405129

申请日：2021-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyoung OH

IPC: H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a package substrate having a first insulating layer, a wiring layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and covering at least a portion of the wiring layer, a pair of support members disposed to face each other on the second insulating layer of the package substrate, and a pair of semiconductor chips disposed between the pair of support members and electrically connected to the wiring layer, wherein the second insulating layer has an opening surrounding at least a portion of each of the pair of semiconductor chips.

公开(公告)号：US20240419013A1

公开(公告)日：2024-12-19

申请号：US18821321

申请日：2024-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjae HWANG ,  Jooyoung OH

IPC: G02B27/64 ,  G03B5/00 ,  G03B30/00 ,  H02K41/035 ,  H04N23/68

Abstract: An electronic device, according to one embodiment, comprises: a housing which forms the exterior of the electronic device, and a camera module which has at least a portion thereof disposed inside the housing. The camera module comprises: a fixed part which is fixedly disposed in the electronic device, a movable part which is connected to a lens or an image sensor and is movable with respect to the fixed part, and an actuator which comprises a magnet unit and a coil unit disposed so as to face each other, and which moves the movable part relative to the fixed part. The coil unit may comprise a first coil layer which comprises a coil having a first coil turn cross-sectional area, and a second coil layer which is positioned relatively farther from the magnet unit than the first coil layer, and comprises a coil having a second coil turn cross-sectional area greater than the first coil turn cross-sectional area. Other various embodiments are possible.

公开(公告)号：US20240063144A1

公开(公告)日：2024-02-22

申请号：US18309179

申请日：2023-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyoung OH

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L25/0657 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49811 ,  H01L23/49894 ,  H01L24/48 ,  H01L24/16 ,  H01L2224/48227 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73265 ,  H01L24/73

Abstract: A semiconductor package includes a substrate having a lower surface and an opposite upper surface, an insulating layer, and a wiring layer on the insulating layer. A first upper protective layer is on the upper surface and includes first openings. A second upper protective layer is on the first upper protective layer. A semiconductor chip is on the first upper protective layer and includes connection pads electrically connected to the wiring layer through the first openings. An encapsulant seals at least a portion of the semiconductor chip, and the second upper protective layer. The first upper protective layer includes a first insulating material. The second upper protective layer includes a second insulating material having a coefficient of thermal expansion lower than that of the first insulating material and a tensile strength higher than that of the first insulating material.

公开(公告)号：US20230098993A1

公开(公告)日：2023-03-30

申请号：US17720064

申请日：2022-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyoung OH

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a package substrate, a first semiconductor chip and a second semiconductor chip sequentially stacked on the package substrate, the first semiconductor chip and the second semiconductor chip being disposed in a form of an offset stack structure, and the second semiconductor chip including an overhang further protruding beyond a side surface of the first semiconductor chip in a first horizontal direction, an adhesive member disposed on a lower surface of the second semiconductor chip, the adhesive member including an extension extending to a lower level than an upper surface of the first semiconductor chip. The extension contacts the side surface of the first semiconductor chip, and overlaps with at least a portion of the overhang in a vertical direction.