公开(公告)号：US20250081468A1

公开(公告)日：2025-03-06

申请号：US18821055

申请日：2024-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Min CHOI ,  Chang Heon LEE ,  Ju Seong MIN ,  Taek Kyu YOON

IPC: H10B43/40 ,  G11C5/06 ,  G11C16/04 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Provided a semiconductor memory device. The semiconductor memory device comprises a cell structure, and a peripheral circuit structure electrically connected to the cell structure. The cell structure includes a plurality of gate electrodes stacked in a vertical direction and spaced apart from each other in the vertical direction, a channel structure penetrating the plurality of gate electrodes in the vertical direction, and a bit-line connected to the channel structure. The peripheral circuit structure includes an active area, a gate structure on the active area, the gate structure intersecting the active area, a source/drain area on at least one side of the gate structure and in the active area, an insulating spacer covering the gate structure, a conductive spacer on a sidewall of the insulating spacer and electrically connected to the source/drain area, and a contact electrically connected to the conductive spacer. At least a portion of a topmost surface of the insulating spacer is coplanar with at least a portion of a topmost surface of the conductive spacer.

公开(公告)号：US20250040140A1

公开(公告)日：2025-01-30

申请号：US18603505

申请日：2024-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Seong MIN ,  Jun Gyeom KIM ,  Hyun Min KIM ,  Kang-Oh YUN ,  Taek Kyu YOON ,  Dong Jin LEE ,  Jae Duk LEE ,  Jee Hoon HAN

IPC: H10B43/40 ,  G11C5/06 ,  G11C16/04 ,  H01L25/065 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor memory device comprises a cell structure and a peripheral circuit structure electrically connected to the cell structure. The peripheral circuit structure comprises an active region, a first gate structure comprising a first gate insulating layer intersecting the active region and in contact with the active region, a second gate structure comprising a second gate insulating layer spaced apart from the first gate structure, and in contact with the active region, and a source/drain region between the first gate structure and the second gate structure. A thickness of the first gate insulating layer is less than a thickness of the second gate insulating layer. The source/drain region comprises a first region adjacent to the first gate structure and a second region adjacent to the second gate structure. A depth of the first region is equal to a depth of the second region.

公开(公告)号：US20230039511A1

公开(公告)日：2023-02-09

申请号：US17729477

申请日：2022-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Seong MIN ,  Jae-Bok BAEK ,  Jee Hoon HAN

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes a lower insulating film that includes a first and second trenches on a substrate, a first wiring in the first trench, a second wiring in the second trench, a capping insulating film including an insulating recess portion and an insulating liner portion, an upper insulating film on the capping insulating film, and an upper contact that penetrates the capping insulating film and connects to the first wiring, The insulating recess portion is in the second trench and the insulating liner portion extends along an upper surface of the lower insulating film. The upper contact includes a contact recess portion in the first trench, an extended portion connected to the contact recess portion, and a plug portion connected to the extended portion inside the upper insulating film. A width of the extended portion is greater than a width of the plug portion.