公开(公告)号：US10109676B2

公开(公告)日：2018-10-23

申请号：US15293771

申请日：2016-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon Bak ,  Woo-Jin Kim ,  Mina Lee ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10

Abstract: A magnetic tunnel junction (MTJ) structure includes a fixed layer pattern structure having a perpendicular magnetization direction, a tunnel barrier pattern on the fixed layer pattern structure, a free layer pattern on the tunnel barrier pattern, the free layer pattern having a perpendicular magnetization direction, a first surface magnetism induction pattern on the free layer pattern, the first surface magnetism induction pattern inducing a perpendicular magnetism in a surface of the free layer pattern, a conductive pattern on the first surface magnetism induction pattern, and a ferromagnetic pattern on the conductive pattern.

公开(公告)号：US11462679B2

公开(公告)日：2022-10-04

申请号：US17038779

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Bak ,  Myoung-Su Son ,  Jae-Chul Shim ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.

公开(公告)号：US10833250B2

公开(公告)日：2020-11-10

申请号：US16045824

申请日：2018-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Bak ,  Myoung-Su Son ,  Jae-Chul Shim ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.