公开(公告)号：US20210159113A1

公开(公告)日：2021-05-27

申请号：US17144226

申请日：2021-01-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungdeog CHOI ,  JungWoo SEO ,  Sangyeon HAN ,  Hyun-Woo CHUNG ,  Hongrae KIM ,  Yoosang HWANG

IPC: H01L21/768 ,  H01L23/498 ,  H01L27/22 ,  H01L27/24 ,  H01L45/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108

Abstract: A semiconductor device includes a pair of line patterns disposed on a substrate. A contact plug is disposed between the pair of line patterns and an air gap is disposed between the contact plug and the line patterns. A landing pad extends from a top end of the contact plug to cover a first part of the air gap and an insulating layer is disposed on a second part of the air gap, which is not covered by the landing pad.

公开(公告)号：US20200013668A1

公开(公告)日：2020-01-09

申请号：US16577429

申请日：2019-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungdeog CHOI ,  JungWoo SEO ,  Sangyeon HAN ,  Hyun-Woo CHUNG ,  Hongrae KIM ,  Yoosang HWANG

IPC: H01L21/768 ,  H01L23/498 ,  H01L27/22 ,  H01L27/24 ,  H01L45/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108

Abstract: A semiconductor device includes bit line structures on a substrate, the bit line structures extending along a first direction and being spaced apart from each other along a second direction perpendicular to the first direction, contact plugs spaced apart from each other along the first direction and being on active regions of the substrate between adjacent bit line structures, a linear spacer on each longitudinal sidewall of a bit line structure, landing pads on the contact plugs, respectively, the landing pads being electrically connected to the contact plugs, respectively, and landing pads that are adjacent to each other along the first direction being offset with respect to each other along the second direction, as viewed in a top view, a conductive pad between each of the contact plugs and a corresponding active region, a vertical axes of the conductive pad and corresponding active region being horizontally offset.

公开(公告)号：US20140322916A1

公开(公告)日：2014-10-30

申请号：US14325080

申请日：2014-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： JungWoo SEO ,  JinSeo CHOI ,  KyoungRyul YOON

IPC: H01L21/308

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76816

Abstract: A semiconductor device is fabricated by forming first holes arranged along a first direction on an etch-target layer, forming dielectric patterns in the first holes, conformally forming a barrier layer on the dielectric patterns, forming a sacrificial layer on the barrier layer to define a first void, partially removing the sacrificial layer to expose the first void, anisotropically etching the barrier layer to form second holes below the first void, and etching portions of the etch-target layer located below the first and second holes to form contact holes. The first void may be formed on a first gap region confined by at least three of the dielectric patterns disposed adjacent to each other, and the sacrificial layer may include a material having a low conformality.

Abstract translation: 通过在蚀刻目标层上形成沿着第一方向布置的第一孔来形成半导体器件，在第一孔中形成电介质图案，在电介质图案上保形地形成阻挡层，在阻挡层上形成牺牲层， 第一空隙，部分地去除牺牲层以暴露第一空隙，各向异性地蚀刻阻挡层以在第一空隙下形成第二孔，以及蚀刻位于第一孔和第二孔下方的蚀刻靶层的部分以形成接触孔。 可以在由彼此相邻布置的至少三个电介质图案限制的第一间隙区域上形成第一空隙，并且牺牲层可以包括具有低共形性的材料。

公开(公告)号：US20140057440A1

公开(公告)日：2014-02-27

申请号：US13956556

申请日：2013-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsoo PARK ,  JungWoo SEO ,  KyoungRyul YOON ,  Cheolhong KIM ,  Seokwoo NAM ,  Yongjik PARK

IPC: H01L21/302

CPC classification number: H01L21/302 ,  H01L21/0337

Abstract: A method of forming a semiconductor device includes first preliminary holes over an etch target, the first preliminary holes arranged as a plurality of rows in a first direction, forming dielectric patterns each filling one of the first preliminary holes, sequentially forming a barrier layer and a sacrificial layer on the dielectric patterns, forming etch control patterns between the dielectric patterns, forming second preliminary holes by etching the sacrificial layer, each of the second preliminary holes being in a region defined by at least three dielectric patterns adjacent to each other, and etching the etch target layer corresponding to positions of the first and second preliminary holes to form contact holes.

Abstract translation: 形成半导体器件的方法包括在蚀刻靶上的第一预备孔，第一预备孔在第一方向上排列成多行，形成各自填充一个第一预备孔的电介质图案，依次形成阻挡层和 在电介质图案上形成牺牲层，在电介质图案之间形成蚀刻控制图案，通过蚀刻牺牲层形成第二预备孔，每个第二预备孔位于由彼此相邻的至少三个电介质图案限定的区域中，以及蚀刻 所述蚀刻目标层对应于所述第一和第二预备孔的位置以形成接触孔。