公开(公告)号：US20250022760A1

公开(公告)日：2025-01-16

申请号：US18635180

申请日：2024-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyun ROH ,  Honggyun KIM ,  Manhee HAN ,  Jaeyoung HONG

IPC: H01L21/66

Abstract: A semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface. The semiconductor substrate includes a circuit pattern region and a peripheral region surrounding the circuit pattern region, an activation layer on the second surface of the semiconductor substrate and having a plurality of circuit patterns in the circuit pattern region, and at least one scattering detection pattern in the peripheral region and having a plurality of circuit cells that generate leakage current based on a scattered beam or heat of a laser.

公开(公告)号：US20230339071A1

公开(公告)日：2023-10-26

申请号：US17977018

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyun ROH ,  Jongguw KIM ,  Wangsun LIM ,  Manhee HAN ,  Jaeyoung HONG

IPC: B24B53/00 ,  B24B53/017 ,  H01L21/304

CPC classification number: B24B53/005 ,  B24B53/017 ,  H01L21/304

Abstract: A grinding apparatus and a method for manufacturing a semiconductor device using the same are provided. A griding apparatus includes a chuck unit configured to receive a substrate, a grinding unit on a part of the chuck unit and configured to grind the substrate, and a dressing unit under a part of the grinding unit adjacent to the chuck unit and including a dressing board configured to dress the grinding unit and magnets under the dressing board.

公开(公告)号：US20220375953A1

公开(公告)日：2022-11-24

申请号：US17570828

申请日：2022-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyun ROH

IPC: H01L27/11526 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device including a peripheral circuit structure on a substrate, a horizontal layer on the peripheral circuit structure, an electrode structure including electrodes on the horizontal layer, the electrodes including pads arranged in a stepwise shape, a planarization insulating layer covering the pads, a contact plug penetrating the planarization insulating layer and coupled to one of the pads, a penetration via penetrating the planarization insulating layer and coupled to the peripheral circuit structure, and a vertical conductive structure between the electrode structure and the penetration via may be provided. The vertical conductive structure may have a bottom surface located at a level that is higher than a top surface of the horizontal layer and is lower than a bottom end of the contact plug.