公开(公告)号：US20240055413A1

公开(公告)日：2024-02-15

申请号：US18195536

申请日：2023-05-10

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Gunho CHANG

IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L25/105 ,  H01L24/73 ,  H01L24/17 ,  H01L24/16 ,  H01L23/5384 ,  H01L24/33 ,  H01L24/32 ,  H01L23/49827 ,  H01L23/3107 ,  H10B80/00 ,  H01L2924/1433 ,  H01L2224/1703 ,  H01L2224/73204 ,  H01L2224/33051 ,  H01L2224/32225 ,  H01L2224/32058 ,  H01L2924/1432 ,  H01L2224/16145 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2224/32145 ,  H01L2224/16227

摘要： A semiconductor package includes a first semiconductor chip, a chip stack on the first semiconductor chip, and a mold layer enclosing the chip stack, on the first semiconductor chip. The chip stack includes second semiconductor chips vertically stacked on the first semiconductor chip, a third semiconductor chip on the second semiconductor chips, and non-conductive layers filling spaces between adjacent ones of the second semiconductor chips. The mold layer fills spaces between the first semiconductor chip and the chip stack, which are spaced apart from each other by a first distance, and between the uppermost one of the second semiconductor chips and the third semiconductor chip, which are spaced apart from each other by a second distance. The second semiconductor chips are spaced apart from each other by a third distance that is smaller than the first distance and the second distance.

公开(公告)号：US11854945B2

公开(公告)日：2023-12-26

申请号：US16228378

申请日：2018-12-20

申请人： Tahoe Research, Ltd.

发明人： Omkar G. Karhade ,  Nitin A. Deshpande ,  Rajendra C. Dias ,  Edvin Cetegen ,  Lars D. Skoglund

IPC分类号： H01L23/485 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/485 ,  H01L21/563 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17505 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/73204 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/00 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/81203 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665

摘要： Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.

公开(公告)号：US11776868B2

公开(公告)日：2023-10-03

申请号：US18123553

申请日：2023-03-20

申请人： Laird Technologies, Inc.

发明人： Jason L. Strader ,  Richard F. Hill

IPC分类号： H01L23/31 ,  H01L23/367 ,  H01L23/42 ,  H01L23/427 ,  H01L23/373 ,  H01L23/00 ,  B23P15/26

CPC分类号： H01L23/3672 ,  B23P15/26 ,  H01L23/3107 ,  H01L23/373 ,  H01L23/42 ,  H01L23/427 ,  H01L24/27 ,  H01L24/32 ,  H01L2224/27426 ,  H01L2224/32058 ,  H01L2224/32245 ,  H01L2924/0002 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/16235 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to various aspects, exemplary embodiments are disclosed of thermal interface materials, electronic devices, and methods for establishing thermal joints between heat spreaders or lids and heat sources. In exemplary embodiments, a method of establishing a thermal joint for conducting heat between a heat spreader and a heat source of an electronic device generally includes positioning a thermal interface material (TIM1) between the heat spreader and the heat source.

公开(公告)号：US20230207573A1

公开(公告)日：2023-06-29

申请号：US18055403

申请日：2022-11-14

申请人： Samsung Display Co., Ltd.

发明人： JI WOONG CHOI ,  Han Bum Kwon

IPC分类号： H01L27/12 ,  H01L25/16 ,  H01L23/00

CPC分类号： H01L27/124 ,  H01L25/167 ,  H01L24/05 ,  H01L24/29 ,  H01L24/13 ,  H01L24/73 ,  H01L24/32 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05073 ,  H01L2224/05022 ,  H01L2224/05573 ,  H01L2224/05562 ,  H01L2224/811 ,  H01L2224/81948 ,  H01L2224/13028 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/1357 ,  H01L2224/1369 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32155 ,  H01L2224/32058 ,  H01L2224/73153 ,  H01L2224/73203 ,  H01L2224/81201 ,  H01L2224/8388

摘要： A display includes a wiring pad and a dummy pad on a first substrate. A first planarization layer is disposed on the wiring pad and the dummy pad. A first pad electrode layer is connected to the wiring pad and a second pad electrode layer is connected to the dummy pad. The first and second pad electrode layers are disposed on the first planarization layer. A first insulating layer covers the first and second pad electrode layers. A first pad electrode upper layer is disposed on the first pad electrode layer. A second pad electrode upper layer is disposed on the second pad electrode layer. The wiring pad, the first pad electrode layer, and the first pad electrode upper layer are electrically connected. The dummy pad, the second pad electrode layer, and the second pad electrode upper layer are electrically connected.

公开(公告)号：US11676930B2

公开(公告)日：2023-06-13

申请号：US17315102

申请日：2021-05-07

申请人： Texas Instruments Incorporated

发明人： Benjamin Stassen Cook ,  Daniel Lee Revier ,  Sadia Naseem ,  Mahmud Halim Chowdhury

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L24/32 ,  H01L24/83 ,  H01L2224/32058 ,  H01L2924/35121

摘要： In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles.

公开(公告)号：US20230145182A1

公开(公告)日：2023-05-11

申请号：US17984502

申请日：2022-11-10

申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.

发明人： Hitoshi Ito ,  Kenichi Koi

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L25/07 ,  H01L25/065 ,  H01L21/48

CPC分类号： H01L23/49844 ,  H01L24/32 ,  H01L25/074 ,  H01L25/0657 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/4985 ,  H01L21/4839 ,  H01L21/4825 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2924/30107 ,  H01L2225/06524 ,  H01L2225/06572 ,  H01L2225/06562

摘要： A semiconductor device includes: a first semiconductor element; a second semiconductor element; a first insulating base member adhesively bonded to the first semiconductor element; a first wiring connected to a first electrode of the first semiconductor element, and disposed on the first insulating base member; a second insulating base member adhesively bonded to the second semiconductor element, a second wiring connected to a third electrode of the second semiconductor element, and disposed on the second insulating base member; a first wiring member connected to a second electrode of the first semiconductor element; a second wiring member electrically connected to the first wiring and a fourth electrode of the second semiconductor element; and a third wiring member connected to the second wiring. A current flows in a first direction in the first wiring member, and flows in a second direction opposite to the first direction in the third wiring member.

公开(公告)号：US20180331022A1

公开(公告)日：2018-11-15

申请号：US15948190

申请日：2018-04-09

申请人： TAIWAN SEMICONDUCTOR CO., LTD.

发明人： Reyn QIN ,  Lucy FAN ,  Meifang SONG ,  Xiaoli WANG

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/13

CPC分类号： H01L23/49517 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/561 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/291 ,  H01L2224/32058 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/3701 ,  H01L2224/37012 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/73263 ,  H01L2224/83907 ,  H01L2224/84345 ,  H01L2224/84385 ,  H01L2224/9221 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/84

摘要： A die package component with a jumper structure includes a first lead frame, a second lead frame, a die, a jumper structure and a package body. The first lead frame has a die connection surface. The second lead frame is separated to the first lead frame. The second lead frame has a lead frame connection groove which defines a thermal deformation tolerance allowable route. The jumper structure is thermally deformed in a thermal-variable environment. The jumper structure includes a die welding portion and a lead welding portion. The die welding portion is welded to the die. Upon meeting a thermal deformation, the lead welding portion would be movable welded along the thermal deformation tolerance allowable route to the lead frame connection groove.

公开(公告)号：US09890036B2

公开(公告)日：2018-02-13

申请号：US15429636

申请日：2017-02-10

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： John Charles Ehmke ,  Virgil Cotoco Ararao

IPC分类号： H01L21/00 ,  H01L21/31 ,  H01L21/469 ,  B81B7/00 ,  B81C1/00 ,  G02B26/08 ,  G02B6/42 ,  G02B26/00 ,  B82Y30/00

CPC分类号： B81B7/0038 ,  B81B2203/0315 ,  B81C1/00269 ,  B81C1/00285 ,  B81C1/00293 ,  B81C2201/0108 ,  B81C2201/013 ,  B81C2201/0188 ,  B81C2201/0198 ,  B81C2201/053 ,  B81C2203/0109 ,  B81C2203/0118 ,  B81C2203/019 ,  B81C2203/035 ,  B82Y30/00 ,  G02B6/4204 ,  G02B6/4208 ,  G02B6/4248 ,  G02B26/001 ,  G02B26/0833 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/039 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05109 ,  H01L2224/05123 ,  H01L2224/05138 ,  H01L2224/05163 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05562 ,  H01L2224/27462 ,  H01L2224/2747 ,  H01L2224/279 ,  H01L2224/29006 ,  H01L2224/29011 ,  H01L2224/29023 ,  H01L2224/29109 ,  H01L2224/29144 ,  H01L2224/32058 ,  H01L2224/32227 ,  H01L2224/83121 ,  H01L2224/83193 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01074 ,  H01L2924/1461 ,  H01L2924/164 ,  H01L2924/00014 ,  H01L2924/01049 ,  H01L2224/03 ,  H01L2924/01042 ,  H01L2924/01072 ,  H01L2924/01004 ,  H01L2224/83 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03462

摘要： In described examples, a hermetic package of a microelectromechanical system (MEMS) structure includes a substrate having a surface with a MEMS structure of a first height. The substrate is hermetically sealed to a cap forming a cavity over the MEMS structure. The cap is attached to the substrate surface by a vertical stack of metal layers adhering to the substrate surface and to the cap. The stack has a continuous outline surrounding the MEMS structure while spaced from the MEMS structure by a distance. The stack has: a first bottom metal seed film adhering to the substrate and a second bottom metal seed film adhering to the first bottom metal seed film; and a first top metal seed film adhering to the cap and a second top metal seed film adhering to the first top metal seed film.

公开(公告)号：US09837368B2

公开(公告)日：2017-12-05

申请号：US14496049

申请日：2014-09-25

申请人： Maxim Integrated Products, Inc.

发明人： Peter R. Harper ,  Martin Mason ,  Arkadii V. Samoilov

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L24/14 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/03334 ,  H01L2224/0346 ,  H01L2224/0384 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05005 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/131 ,  H01L2224/16058 ,  H01L2224/161 ,  H01L2224/291 ,  H01L2224/32058 ,  H01L2224/321 ,  H01L2224/85 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/0645 ,  H01L2924/0665 ,  H01L2924/0695 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

摘要： A wafer level package device, electronic device, and fabrication methods for fabrication of the wafer level package device are described that include forming an exposed lead tip on the wafer level package for providing a solder buttress structure when coupling the wafer level package device to another electrical component. In implementations, the wafer level package device includes at least one integrated circuit die, a metal pad, a first dielectric layer, a redistribution layer, a second dielectric layer, a pillar structure, a molding layer, a pillar layer, and a plating layer, where the pillar layer is sawn to form pad contacts on at least two sides of the wafer level package device. The exposed pad contact facilitate a solder fillet and buttress structure resulting in improved board level reliability.

公开(公告)号：US09716060B2

公开(公告)日：2017-07-25

申请号：US14692769

申请日：2015-04-22

申请人： Siliconware Precision Industries Co., Ltd.

发明人： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC分类号： H01L23/498 ,  H05K3/00 ,  H05K3/32 ,  H05K1/18 ,  H01L23/538 ,  H01L23/00 ,  H05K1/02 ,  H05K3/10 ,  H05K3/46 ,  H01L23/31 ,  H01L21/683

CPC分类号： H01L23/49838 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/189 ,  H05K3/0026 ,  H05K3/007 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665

摘要： The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.