公开(公告)号：US20230082884A1

公开(公告)日：2023-03-16

申请号：US17748654

申请日：2022-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongbeom KO

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes a base redistribution layer, a first semiconductor chip on the base redistribution layer, at least two chip stacks stacked on the first semiconductor chip and each including a plurality of second semiconductor chips, a first molding layer covering an upper surface of the first semiconductor chip and surrounding the at least two chip stacks, a third semiconductor chip between the base redistribution layer and the first semiconductor chip, a plurality of connection posts between the base redistribution layer and the first semiconductor chips paced apart from the third semiconductor chip in a horizontal direction, and a second molding layer surrounding the third semiconductor chip and the plurality of connection posts between the base redistribution layer and the first semiconductor chip.

公开(公告)号：US20220415842A1

公开(公告)日：2022-12-29

申请号：US17537994

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongbeom KO ,  Wooju KIM ,  Heejae NAM ,  Jungseok RYU ,  Haemin PARK

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a semiconductor chip on a substrate. The semiconductor chip includes an active region, and a scribe lane in continuity with an edge of the active region. A non-conductive film (NCF) is between the substrate and the semiconductor chip, the non-conductive film (NCF) at least partially defines a recess region overlapping with the scribe lane in plan view and extending on the active region.

公开(公告)号：US20240297141A1

公开(公告)日：2024-09-05

申请号：US18659400

申请日：2024-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongbeom KO ,  Wooju KIM ,  Heejae NAM ,  Jungseok RYU ,  Haemin PARK

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/32 ,  H01L25/0657 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/32057 ,  H01L2224/32058 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2924/10156

Abstract: A semiconductor package includes a semiconductor chip on a substrate. The semiconductor chip includes an active region, and a scribe lane in continuity with an edge of the active region. A non-conductive film (NCF) is between the substrate and the semiconductor chip, the non-conductive film (NCF) at least partially defines a recess region overlapping with the scribe lane in plan view and extending on the active region.

公开(公告)号：US20240413026A1

公开(公告)日：2024-12-12

申请号：US18658546

申请日：2024-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongbeom KO ,  Seokgeun Ahn ,  Juhyeon Oh ,  Sanghoon Lee ,  Gwangjae Jeon

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes a buffer die, a plurality of core die blocks sequentially stacked on the buffer die, and a molding member on the buffer die and covering outer surfaces of the plurality of core die blocks. Each of the plurality of core die blocks includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and a first gap filling portion, a third semiconductor chip disposed on the second semiconductor chip and a second gap filling portion, and a fourth semiconductor chip disposed on the third semiconductor chip.

公开(公告)号：US20230420352A1

公开(公告)日：2023-12-28

申请号：US18154261

申请日：2023-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongbeom KO ,  Junyun KWEON ,  Wooju KIM ,  Heejae NAM ,  Haemin PARK ,  Junggeun SHIN

IPC: H01L23/498 ,  H10B80/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49833 ,  H10B80/00 ,  H01L24/96 ,  H01L24/97 ,  H01L24/32 ,  H01L24/16 ,  H01L24/73 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3135 ,  H01L2924/182 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2224/95001 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L24/48 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73253

Abstract: A semiconductor package, comprising: a first redistribution structure including a first redistribution via; a first package that is on an upper surface of the first redistribution structure and comprises a first pad; a second redistribution structure that is on a lower surface of the first redistribution structure and comprises a second redistribution via; a second semiconductor chip that is between the first redistribution structure and the second redistribution structure and comprises a connection pad; and a vertical connection structure that is between the first redistribution structure and the second redistribution structure, wherein the vertical connection structure is electrically connected to the first redistribution via and the second redistribution via, the connection pad is electrically connected to the second redistribution via, and the first redistribution via is electrically connected to the first pad.