公开(公告)号：US20230081783A1

公开(公告)日：2023-03-16

申请号：US17804397

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGSOO KIM ,  JINYOUNG PARK ,  KYEN-HEE LEE

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a gate electrode on a channel pattern connected to the source/drain pattern, an active contact on the source/drain pattern, a first lower interconnection line on the active contact, a second lower interconnection line on the gate electrode, a first spacer between the gate electrode and the active contact, and a second spacer between the first spacer and the gate electrode or the active contact. The gate electrode includes an electrode body portion and an electrode protruding portion protruding from a top surface thereof and contacting the second lower interconnection line. The active contact includes a contact body portion and a contact protruding portion protruding from a top surface thereof and contacting the first lower interconnection line. A top surface of the first spacer is higher than a top surface of the second spacer.

公开(公告)号：US20230361119A1

公开(公告)日：2023-11-09

申请号：US18134853

申请日：2023-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYEN-HEE LEE ,  Kyungsoo Kim

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/822 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Disclosed are three-dimensional semiconductor devices and their fabrication methods. The 3D semiconductor device includes a first active region on a substrate and including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern, a second active region above the first active region and including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, at least one gate electrode on the lower and upper channel patterns, a first active contact electrically connected to the lower source/drain pattern, and a second active contact electrically connected to the upper source/drain pattern. A first central line of the lower source/drain pattern and a second central line of the upper source/drain pattern in a vertical direction are offset from each other in a first direction perpendicular to the vertical direction. The first active contact and the second active contact are spaced apart from each other in the first direction.

公开(公告)号：US20230214990A1

公开(公告)日：2023-07-06

申请号：US17900334

申请日：2022-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Cheol KANG ,  SOORYONG LEE ,  KYEN-HEE LEE

IPC: G06T7/00 ,  G06T7/30 ,  G06T11/00

CPC classification number: G06T7/001 ,  G06T7/30 ,  G06T11/00 ,  G06T2207/30148 ,  G06T2207/20084 ,  G06T2207/10061

Abstract: Disclosed is a semiconductor integrated circuit fabricating method of a semiconductor fabricating device which includes a processor executing a defect detection module includes receiving, at the defect detection module, a first capture image of the semiconductor integrated circuit and a first layout image, generating, at the defect detection module, a second layout image from the first capture image, generating, at the defect detection module, a contour image from the first capture image and the second layout image, detecting, at the defect detection module, a defect of the semiconductor integrated circuit based on the first layout image and the contour image, analyzing, at the semiconductor fabricating device, a correlation between a kind of the defect and process variations of the semiconductor integrated circuit, and changing, at the semiconductor fabricating device, at least one process variation having a correlation with the defect from among the process variations.