公开(公告)号：US20130235685A1

公开(公告)日：2013-09-12

申请号：US13788453

申请日：2013-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hong Beom Kim ,  Kab Yong Kim

IPC: G11C29/08

CPC classification number: G11C29/08 ,  G11C5/145 ,  G11C8/08 ,  G11C29/025 ,  G11C29/12005 ,  G11C2029/1202

Abstract: A semiconductor memory device may include a voltage comparator, a voltage generator, a counter, and a circuit. The voltage comparator may be configured to generate an enabling signal responsive to a comparison indicating that a first voltage is lower than a reference voltage. The voltage generator may be configured to generate oscillation signals and a boost voltage by boosting the first voltage and to feed the boost voltage back as the first voltage in response to the enabling signal. The counter may be configured to count the number of the oscillation signals, and to generate a count output signal having information corresponding to the number of the oscillation signals. The circuit may be configured to output the count output signal as a quality output signal indicating the counted number relative to a target set value.

Abstract translation: 半导体存储器件可以包括电压比较器，电压发生器，计数器和电路。 电压比较器可以被配置为响应于指示第一电压低于参考电压的比较来产生使能信号。 电压发生器可以被配置为通过升高第一电压并响应于使能信号而将升压电压反馈回作为第一电压来产生振荡信号和升压电压。 计数器可以被配置为对振荡信号的数量进行计数，并且产生具有与振荡信号的数量相对应的信息的计数输出信号。 电路可以被配置为输出计数输出信号作为指示相对于目标设定值的计数的质量输出信号。

公开(公告)号：US09076549B2

公开(公告)日：2015-07-07

申请号：US14213566

申请日：2014-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Jeong Kim ,  Kab Yong Kim ,  Kwang Woo Lee ,  Heon Lee ,  In Ho Cho

IPC: G11C11/406 ,  G11C29/00

CPC classification number: G11C11/40618 ,  G11C11/40603 ,  G11C29/70 ,  G11C29/783 ,  G11C2211/4061

Abstract: A semiconductor memory device includes: a normal memory cell block including a first plurality of memory cells; a redundancy memory cell block including a second plurality of memory cells and configured for use in replacing memory cells of the normal memory cell block; a weak cell information storage configured to store information regarding weak memory cells in the normal and redundancy memory cell blocks; and a refresh control circuit configured to control a refresh rate of memory cells in the normal and redundancy memory cell blocks based on the information regarding weak memory cells in the weak cell information storage. The weak memory cells in the normal and redundancy memory cell blocks are refreshed at least once more than other memory cells in the normal and redundancy memory cell blocks during a refresh cycle.

Abstract translation: 半导体存储器件包括：包括第一多个存储器单元的正常存储器单元块; 包括第二多个存储单元并被配置为用于替换正常存储器单元块的存储单元的冗余存储单元块; 弱电池信息存储器，被配置为存储关于正常和冗余存储器单元块中的弱存储器单元的信息; 以及刷新控制电路，被配置为基于关于弱小区信息存储器中的弱存储器单元的信息来控制正常和冗余存储器单元块中的存储器单元的刷新率。 在刷新周期期间，正常和冗余存储单元块中的弱存储器单元至少比正常和冗余存储器单元块中的其它存储器单元更新一次。