公开(公告)号：US09076549B2

公开(公告)日：2015-07-07

申请号：US14213566

申请日：2014-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Jeong Kim ,  Kab Yong Kim ,  Kwang Woo Lee ,  Heon Lee ,  In Ho Cho

IPC: G11C11/406 ,  G11C29/00

CPC classification number: G11C11/40618 ,  G11C11/40603 ,  G11C29/70 ,  G11C29/783 ,  G11C2211/4061

Abstract: A semiconductor memory device includes: a normal memory cell block including a first plurality of memory cells; a redundancy memory cell block including a second plurality of memory cells and configured for use in replacing memory cells of the normal memory cell block; a weak cell information storage configured to store information regarding weak memory cells in the normal and redundancy memory cell blocks; and a refresh control circuit configured to control a refresh rate of memory cells in the normal and redundancy memory cell blocks based on the information regarding weak memory cells in the weak cell information storage. The weak memory cells in the normal and redundancy memory cell blocks are refreshed at least once more than other memory cells in the normal and redundancy memory cell blocks during a refresh cycle.

Abstract translation: 半导体存储器件包括：包括第一多个存储器单元的正常存储器单元块; 包括第二多个存储单元并被配置为用于替换正常存储器单元块的存储单元的冗余存储单元块; 弱电池信息存储器，被配置为存储关于正常和冗余存储器单元块中的弱存储器单元的信息; 以及刷新控制电路，被配置为基于关于弱小区信息存储器中的弱存储器单元的信息来控制正常和冗余存储器单元块中的存储器单元的刷新率。 在刷新周期期间，正常和冗余存储单元块中的弱存储器单元至少比正常和冗余存储器单元块中的其它存储器单元更新一次。

公开(公告)号：US11915782B2

公开(公告)日：2024-02-27

申请号：US17407585

申请日：2021-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Min Lee ,  Nam Hyung Kim ,  Dae Jeong Kim ,  Do Han Kim ,  Min Su Kim ,  Deok Ho Seo ,  Won Jae Shin ,  Yong Jun Yu ,  Il Gyu Jung ,  In Su Choi

IPC: G11C7/10 ,  G11C8/18 ,  G11C7/14

CPC classification number: G11C7/1063 ,  G11C7/109 ,  G11C7/1012 ,  G11C7/14 ,  G11C8/18

Abstract: An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.