公开(公告)号：US10332587B1

公开(公告)日：2019-06-25

申请号：US15986354

申请日：2018-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Jong Sung ,  Dae Sun Kim ,  Jin Seon Kim ,  In Cheol Nam

IPC: G11C11/24 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4099

Abstract: A dynamic random access memory (DRAM) device includes a memory cell array including a first sub memory cell array block including a plurality of first memory cells between a plurality of first sub word lines, and a plurality of first odd-numbered bit lines and a plurality of dummy bit lines and includes a second sub memory cell array block including a plurality of second memory cells between a plurality of second sub word lines, a plurality of second odd-numbered bit lines, and a plurality of second even-numbered bit lines. The memory cell array may be arranged to have an open bit line architecture in which the plurality of first odd-numbered bit lines and the plurality of second even-numbered bit lines form bit line pairs. When the first sub word line may be selected, a predetermined voltage may be applied to the plurality of dummy bit lines for a first predetermined period in which a charge sharing operation is performed on the plurality of first memory cells connected to the selected one of the plurality of first sub word lines.

公开(公告)号：US20190180812A1

公开(公告)日：2019-06-13

申请号：US15986354

申请日：2018-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Jong Sung ,  Dae Sun Kim ,  Jin Seon Kim ,  In Cheol Nam

IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4099 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C11/4094 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4099

Abstract: A dynamic random access memory (DRAM) device includes a memory cell array including a first sub memory cell array block including a plurality of first memory cells between a plurality of first sub word lines, and a plurality of first odd-numbered bit lines and a plurality of dummy bit lines and includes a second sub memory cell array block including a plurality of second memory cells between a plurality of second sub word lines, a plurality of second odd-numbered bit lines, and a plurality of second even-numbered bit lines. The memory cell array may be arranged to have an open bit line architecture in which the plurality of first odd-numbered bit lines and the plurality of second even-numbered bit lines form bit line pairs. When the first sub word line may be selected, a predetermined voltage may be applied to the plurality of dummy bit lines for a first predetermined period in which a charge sharing operation is performed on the plurality of first memory cells connected to the selected one of the plurality of first sub word lines.