公开(公告)号：US20210249382A1

公开(公告)日：2021-08-12

申请号：US17015346

申请日：2020-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihong JEONG ,  Sangsub SONG

IPC: H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a package substrate, a processor chip mounted on the package substrate, a first stack structure on the package substrate, the first stack structure including a number M of memory chips stacked on the processor chip, and a second stack structure on the package substrate and spaced apart from the processor chip, the second stack structure including a number N of memory chips stacked on the package substrate. A number Q of channels that electrically connect the memory chips of the second stack structure with the processor chip may be greater than a number P of channels that electrically connect the memory chips of the first stack structure with the processor chip, or the number N of memory chips included in the second stack structure may be greater than the number M of memory chips included in the first stack structure.

公开(公告)号：US20210103791A1

公开(公告)日：2021-04-08

申请号：US16935374

申请日：2020-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Injae LEE ,  Sangsub SONG ,  Minkyung KOOK ,  Kihong JEONG

IPC: G06K19/077 ,  G11C5/14 ,  G11C7/10

Abstract: A card-type solid state drive (SSD) including: a substrate having an insertion edge, a first edge, and a second edge, wherein the first edge and the second edge are adjacent to the insertion edge; a protrusion on the first edge; first column terminals adjacent to the insertion edge and including a first power terminal and first data terminals; second column terminals farther apart from the insertion edge than the first column terminals and including a second power terminal and second data terminals; and third column terminals farther apart from the insertion edge than the second column terminals and including a third power terminal and command terminals, wherein the first, second and third power terminals are arranged along the first edge.

公开(公告)号：US20240234367A1

公开(公告)日：2024-07-11

申请号：US18612474

申请日：2024-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kihong JEONG ,  Sangsub SONG

IPC: H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L25/18 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586

Abstract: A semiconductor package includes a package substrate, a processor chip mounted on the package substrate, a first stack structure on the package substrate, the first stack structure including a number M of memory chips stacked on the processor chip, and a second stack structure on the package substrate and spaced apart from the processor chip, the second stack structure including a number N of memory chips stacked on the package substrate. A number Q of channels that electrically connect the memory chips of the second stack structure with the processor chip may be greater than a number P of channels that electrically connect the memory chips of the first stack structure with the processor chip, or the number N of memory chips included in the second stack structure may be greater than the number M of memory chips included in the first stack structure.

公开(公告)号：US20240113074A1

公开(公告)日：2024-04-04

申请号：US18374437

申请日：2023-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heewoo AN ,  Sangsub SONG ,  Kihong JEONG

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48149 ,  H01L2224/48229 ,  H01L2224/73265 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: Provided is a semiconductor package including a first substrate having an upper surface and a lower surface, and including a substrate pad arranged on the upper surface, a first chip stacked structure mounted on the upper surface of the first substrate, and including a plurality of first chips offset-stacked in a first direction, a lowermost first wire electrically connecting a lowermost first chip to the substrate pad, and a second chip stacked structure mounted on the upper surface of the first substrate, and including a plurality of second chips offset-stacked in the first direction, wherein the second chip stacked structure is spaced apart from the first chip stacked structure with the lowermost first wire therebetween in a horizontal direction, and an upper surface of a lowermost second chip is at a higher vertical direction level than a highest level of the lowermost first wire in a vertical direction.

公开(公告)号：US20230163099A1

公开(公告)日：2023-05-25

申请号：US18101246

申请日：2023-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihong JEONG ,  Sangsub SONG

IPC: H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L25/18 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586

Abstract: A semiconductor package includes a package substrate, a processor chip mounted on the package substrate, a first stack structure on the package substrate, the first stack structure including a number M of memory chips stacked on the processor chip, and a second stack structure on the package substrate and spaced apart from the processor chip, the second stack structure including a number N of memory chips stacked on the package substrate. A number Q of channels that electrically connect the memory chips of the second stack structure with the processor chip may be greater than a number P of channels that electrically connect the memory chips of the first stack structure with the processor chip, or the number N of memory chips included in the second stack structure may be greater than the number M of memory chips included in the first stack structure.