公开(公告)号：US20210249382A1

公开(公告)日：2021-08-12

申请号：US17015346

申请日：2020-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihong JEONG ,  Sangsub SONG

IPC: H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a package substrate, a processor chip mounted on the package substrate, a first stack structure on the package substrate, the first stack structure including a number M of memory chips stacked on the processor chip, and a second stack structure on the package substrate and spaced apart from the processor chip, the second stack structure including a number N of memory chips stacked on the package substrate. A number Q of channels that electrically connect the memory chips of the second stack structure with the processor chip may be greater than a number P of channels that electrically connect the memory chips of the first stack structure with the processor chip, or the number N of memory chips included in the second stack structure may be greater than the number M of memory chips included in the first stack structure.

公开(公告)号：US20240224544A1

公开(公告)日：2024-07-04

申请号：US18512199

申请日：2023-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KIHONG JEONG ,  Sangsub SONG ,  Heewoo AN

IPC: H10B80/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586

Abstract: A processor chip for a semiconductor package includes a substrate having a first surface and a second surface opposite to the first surface and mounted on a package substrate, and a plurality of chip pads disposed on the first surface of the substrate and electrically connected to the package substrate, wherein the first surface is divided into a first area and a second area, the first area includes four sides of the first surface and the second area includes a center of the first surface, and the plurality of chip pads are located on the first area and are arranged on at least a portion of a side of the first surface in a line along the side.

公开(公告)号：US20210103791A1

公开(公告)日：2021-04-08

申请号：US16935374

申请日：2020-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Injae LEE ,  Sangsub SONG ,  Minkyung KOOK ,  Kihong JEONG

IPC: G06K19/077 ,  G11C5/14 ,  G11C7/10

Abstract: A card-type solid state drive (SSD) including: a substrate having an insertion edge, a first edge, and a second edge, wherein the first edge and the second edge are adjacent to the insertion edge; a protrusion on the first edge; first column terminals adjacent to the insertion edge and including a first power terminal and first data terminals; second column terminals farther apart from the insertion edge than the first column terminals and including a second power terminal and second data terminals; and third column terminals farther apart from the insertion edge than the second column terminals and including a third power terminal and command terminals, wherein the first, second and third power terminals are arranged along the first edge.

公开(公告)号：US20210397569A1

公开(公告)日：2021-12-23

申请号：US17172420

申请日：2021-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangsub SONG

IPC: G06F13/16 ,  G06F13/38 ,  G06F13/40

Abstract: An interface device between a plurality of memory devices and a memory controller includes processing circuitry configured to provide a plurality of controller channels for communicating with the memory controller, to provide a plurality of memory channels for communicating with the plurality of memory devices, and to connect each of the plurality of controller channels to at least one of the plurality of memory channels in a first mode and disconnect the plurality of controller channels from the plurality of memory channels in a second mode.

公开(公告)号：US20240234367A1

公开(公告)日：2024-07-11

申请号：US18612474

申请日：2024-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kihong JEONG ,  Sangsub SONG

IPC: H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L25/18 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586

Abstract: A semiconductor package includes a package substrate, a processor chip mounted on the package substrate, a first stack structure on the package substrate, the first stack structure including a number M of memory chips stacked on the processor chip, and a second stack structure on the package substrate and spaced apart from the processor chip, the second stack structure including a number N of memory chips stacked on the package substrate. A number Q of channels that electrically connect the memory chips of the second stack structure with the processor chip may be greater than a number P of channels that electrically connect the memory chips of the first stack structure with the processor chip, or the number N of memory chips included in the second stack structure may be greater than the number M of memory chips included in the first stack structure.

公开(公告)号：US20240113074A1

公开(公告)日：2024-04-04

申请号：US18374437

申请日：2023-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heewoo AN ,  Sangsub SONG ,  Kihong JEONG

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48149 ,  H01L2224/48229 ,  H01L2224/73265 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: Provided is a semiconductor package including a first substrate having an upper surface and a lower surface, and including a substrate pad arranged on the upper surface, a first chip stacked structure mounted on the upper surface of the first substrate, and including a plurality of first chips offset-stacked in a first direction, a lowermost first wire electrically connecting a lowermost first chip to the substrate pad, and a second chip stacked structure mounted on the upper surface of the first substrate, and including a plurality of second chips offset-stacked in the first direction, wherein the second chip stacked structure is spaced apart from the first chip stacked structure with the lowermost first wire therebetween in a horizontal direction, and an upper surface of a lowermost second chip is at a higher vertical direction level than a highest level of the lowermost first wire in a vertical direction.

公开(公告)号：US20230395568A1

公开(公告)日：2023-12-07

申请号：US18116011

申请日：2023-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Buwon KIM ,  Sangsub SONG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L23/3128 ,  H01L2225/06562 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/48145 ,  H01L2224/48465

Abstract: In some embodiments, a semiconductor package includes a package substrate that includes a first surface, a second surface that is opposite to the first surface, first substrate pads disposed on the first surface in a first row, and second substrate pads disposed on the first surface in a second row. The semiconductor package further includes a first semiconductor chip that includes first chip pads, lower bonding wires configured to respectively couple the first chip pads and the first substrate pads, a second semiconductor chip that includes second chip pads, upper bonding wires configured to respectively couple the second chip pads and the second substrate pads, and an encapsulant disposed on the package substrate and covering the first semiconductor chip and the second semiconductor chip. The lower bonding wires are ball-bonded to the first chip pads and stich-bonded to the first substrate pads.

公开(公告)号：US20230163099A1

公开(公告)日：2023-05-25

申请号：US18101246

申请日：2023-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihong JEONG ,  Sangsub SONG

IPC: H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L25/18 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586

Abstract: A semiconductor package includes a package substrate, a processor chip mounted on the package substrate, a first stack structure on the package substrate, the first stack structure including a number M of memory chips stacked on the processor chip, and a second stack structure on the package substrate and spaced apart from the processor chip, the second stack structure including a number N of memory chips stacked on the package substrate. A number Q of channels that electrically connect the memory chips of the second stack structure with the processor chip may be greater than a number P of channels that electrically connect the memory chips of the first stack structure with the processor chip, or the number N of memory chips included in the second stack structure may be greater than the number M of memory chips included in the first stack structure.