公开(公告)号：US10911908B2

公开(公告)日：2021-02-02

申请号：US16646794

申请日：2018-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Hyun Kim ,  Minsun Kim ,  Kisoo Park ,  Young Pil Shin ,  Moonsoo Chang ,  Jonghyun Jin ,  Eunkyung Lee ,  Taihun Kang ,  Wonseok Baek ,  Hyunjin Jo

IPC: H04W4/14 ,  H04L12/58 ,  H04L29/08 ,  H04L29/06

Abstract: Various embodiments of the present invention relate to an electronic device for processing a message and a method for operating the same. The electronic device comprises a display, a wireless communication circuit, a processor operatively connected to the communication circuit and to the display, and a memory operatively connected to the processor. The memory stores a first application program, which is a short message service (SMS) application program, and a second application program, which is a non-SMS application program. The memory may comprise instructions that, when executed, cause the processor to: receive a push notification from an external server through the communication circuit by using the second application program, the push notification indicating a message regarding the first application program; transmit a request regarding the message to the external server through the communication circuit by using the second application program; receive the message from the external server through the communication circuit by using the second application program; provide the message to the first application program by using the second application program; and display the message by using the user interface of the first application program. Other embodiments are also possible.

公开(公告)号：US11631677B2

公开(公告)日：2023-04-18

申请号：US17358055

申请日：2021-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyoung Moon ,  Jamin Koo ,  Kyuwan Kim ,  Kisoo Park

IPC: H01L27/108

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.

公开(公告)号：US12200922B2

公开(公告)日：2025-01-14

申请号：US18116883

申请日：2023-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyoung Moon ,  Jamin Koo ,  Kyuwan Kim ,  Kisoo Park

IPC: H10B12/00

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.

公开(公告)号：US20240105791A1

公开(公告)日：2024-03-28

申请号：US18371869

申请日：2023-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyoung MOON ,  Jamin Koo ,  Kyuwan Kim ,  Jonghyeok Kim ,  Hyokyoung Kim ,  Kisoo Park

IPC: H01L29/423 ,  H10B12/00

CPC classification number: H01L29/4236 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: An integrated circuit device includes a substrate including a plurality of active regions; a plurality of device isolation layers provided in the substrate and defining the plurality of active regions; a plurality of bitlines spaced apart from each other in a first horizontal direction on the substrate and extending in a second horizontal direction crossing the first horizontal direction; a plurality of insulating fences spaced apart from each other in the second horizontal direction and provided between adjacent bitlines of the plurality of bitlines; a plurality of buried contacts connected to the plurality of active regions and provided between adjacent bitlines of the plurality of bitlines and between the plurality of insulating fences; and a plurality of vertical insulating layers vertically positioned between the plurality of insulating fences and the plurality of buried contacts.

公开(公告)号：US20220173107A1

公开(公告)日：2022-06-02

申请号：US17358055

申请日：2021-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyoung Moon ,  Jamin Koo ,  Kyuwan Kim ,  Kisoo Park

IPC: H01L27/108

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.