公开(公告)号：US20230064060A1

公开(公告)日：2023-03-02

申请号：US17744635

申请日：2022-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong Woo LEE ,  Sang Jin YOO ,  Hee-Woong KANG ,  Kwang Woo LEE ,  Hee Won LEE

IPC: H03M13/11 ,  G11C29/52 ,  G11C7/10

Abstract: A method for operating a storage controller includes receiving a first read command, performing a first read of data stored in a nonvolatile memory using a first read level and receiving a first read data, performing first error correction decoding of the first read data to determine whether the first error correction decoding succeeds, determining a second read level using a predetermined method, and determining a first soft decision offset value of the second read level, reading data stored in the nonvolatile memory using the determined second read level and the first soft decision offset value and receiving a first soft decision data, performing second error correction decoding of the first soft decision data to determine whether the second error correction decoding succeeds, and storing the second read level, a first method used to determine the second read level and the first soft decision offset value.

公开(公告)号：US20210072920A1

公开(公告)日：2021-03-11

申请号：US16829660

申请日：2020-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong Woo LEE ,  Chan Ha KIM ,  Kang Ho ROH ,  Kwang Woo LEE ,  Hee Won LEE

IPC: G06F3/06 ,  G06F11/07 ,  G06F11/30 ,  G06F9/455 ,  G06K9/62 ,  G06N20/00

Abstract: A storage device, including a feature information database configured to store feature information about a memory device; and a machine learning module configured to select a machine learning model from a plurality of machine learning models the corresponding to an operation of the memory device based on the feature information, wherein the memory device is configured to operate according to the selected machine learning model.

公开(公告)号：US20140269123A1

公开(公告)日：2014-09-18

申请号：US14213566

申请日：2014-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Jeong KIM ,  Kab Yong KIM ,  Kwang Woo LEE ,  Heon LEE ,  In Ho CHO

IPC: G11C11/406 ,  G11C29/00

CPC classification number: G11C11/40618 ,  G11C11/40603 ,  G11C29/70 ,  G11C29/783 ,  G11C2211/4061

Abstract: A semiconductor memory device includes: a normal memory cell block including a first plurality of memory cells; a redundancy memory cell block including a second plurality of memory cells and configured for use in replacing memory cells of the normal memory cell block; a weak cell information storage configured to store information regarding weak memory cells in the normal and redundancy memory cell blocks; and a refresh control circuit configured to control a refresh rate of memory cells in the normal and redundancy memory cell blocks based on the information regarding weak memory cells in the weak cell information storage. The weak memory cells in the normal and redundancy memory cell blocks are refreshed at least once more than other memory cells in the normal and redundancy memory cell blocks during a refresh cycle.

Abstract translation: 半导体存储器件包括：包括第一多个存储器单元的正常存储器单元块; 包括第二多个存储单元并被配置为用于替换正常存储器单元块的存储单元的冗余存储单元块; 弱电池信息存储器，被配置为存储关于正常和冗余存储器单元块中的弱存储器单元的信息; 以及刷新控制电路，被配置为基于关于弱小区信息存储器中的弱存储器单元的信息来控制正常和冗余存储器单元块中的存储器单元的刷新率。 在刷新周期期间，正常和冗余存储单元块中的弱存储器单元至少比正常和冗余存储器单元块中的其它存储器单元更新一次。