公开(公告)号：US20240194243A1

公开(公告)日：2024-06-13

申请号：US18581018

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-Woong KANG ,  Dong-Hun KWAK ,  Jun-Ho SEO ,  Hee-Won LEE

IPC: G11C11/4074 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C11/4074 ,  G11C7/109 ,  G11C7/12 ,  G11C8/12 ,  G11C11/4082 ,  G11C11/4085 ,  G11C11/4097 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3436 ,  G11C2207/2209

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

公开(公告)号：US20200372945A1

公开(公告)日：2020-11-26

申请号：US16991693

申请日：2020-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-Woong KANG ,  Dong-Hun KWAK ,  Jun-Ho SEO ,  Hee-Won LEE

IPC: G11C11/4074 ,  G11C7/12 ,  G11C7/10 ,  G11C8/12 ,  G11C16/08 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

公开(公告)号：US20200075078A1

公开(公告)日：2020-03-05

申请号：US16675331

申请日：2019-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hun KWAK ,  Hee-Woong KANG ,  Jun-Ho SEO ,  Hee-Won LEE

IPC: G11C11/4074 ,  G11C7/12 ,  G11C7/10 ,  G11C8/12 ,  G11C16/08 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34

Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.

公开(公告)号：US20210272617A1

公开(公告)日：2021-09-02

申请号：US17321393

申请日：2021-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-Woong KANG ,  Dong-Hun KWAK ,  Jun-Ho SEO ,  Hee-Won LEE

IPC: G11C11/4074 ,  G11C7/10 ,  G11C8/12 ,  G11C16/08 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34 ,  G11C7/12

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

公开(公告)号：US20200219552A1

公开(公告)日：2020-07-09

申请号：US16817951

申请日：2020-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hun KWAK ,  Hee-Woong KANG ,  Jun-Ho SEO ,  Hee-Won LEE

IPC: G11C11/4074 ,  G11C16/34 ,  G11C16/30 ,  G11C16/10 ,  G11C16/06 ,  G11C16/04 ,  G11C11/56 ,  G11C11/4097 ,  G11C11/408 ,  G11C16/08 ,  G11C8/12 ,  G11C7/10 ,  G11C7/12

Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.

公开(公告)号：US20230064060A1

公开(公告)日：2023-03-02

申请号：US17744635

申请日：2022-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong Woo LEE ,  Sang Jin YOO ,  Hee-Woong KANG ,  Kwang Woo LEE ,  Hee Won LEE

IPC: H03M13/11 ,  G11C29/52 ,  G11C7/10

Abstract: A method for operating a storage controller includes receiving a first read command, performing a first read of data stored in a nonvolatile memory using a first read level and receiving a first read data, performing first error correction decoding of the first read data to determine whether the first error correction decoding succeeds, determining a second read level using a predetermined method, and determining a first soft decision offset value of the second read level, reading data stored in the nonvolatile memory using the determined second read level and the first soft decision offset value and receiving a first soft decision data, performing second error correction decoding of the first soft decision data to determine whether the second error correction decoding succeeds, and storing the second read level, a first method used to determine the second read level and the first soft decision offset value.

公开(公告)号：US20230036205A1

公开(公告)日：2023-02-02

申请号：US17958386

申请日：2022-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-Woong KANG ,  Dong-Hun KWAK ,  Jun-Ho SEO ,  Hee-Won LEE

IPC: G11C11/4074 ,  G11C7/10 ,  G11C8/12 ,  G11C16/08 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34 ,  G11C7/12

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

公开(公告)号：US20190074048A1

公开(公告)日：2019-03-07

申请号：US16183315

申请日：2018-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hun KWAK ,  Hee-Woong KANG ,  Jun-Ho SEO ,  Hee-Won LEE

IPC: G11C11/4074 ,  G11C7/12 ,  G11C8/12 ,  G11C7/10 ,  G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C16/10 ,  G11C16/30 ,  G11C11/408 ,  G11C11/4097 ,  G11C16/06 ,  G11C16/08

Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.