Abstract:
A semiconductor memory device includes: a normal memory cell block including a first plurality of memory cells; a redundancy memory cell block including a second plurality of memory cells and configured for use in replacing memory cells of the normal memory cell block; a weak cell information storage configured to store information regarding weak memory cells in the normal and redundancy memory cell blocks; and a refresh control circuit configured to control a refresh rate of memory cells in the normal and redundancy memory cell blocks based on the information regarding weak memory cells in the weak cell information storage. The weak memory cells in the normal and redundancy memory cell blocks are refreshed at least once more than other memory cells in the normal and redundancy memory cell blocks during a refresh cycle.
Abstract:
A refresh leveraging driving method is provided which includes deciding a unit of word lines to be driven at a refresh leveraging operation to be the same as a redundancy repair row unit setting a lower row address of an input refresh leveraging address corresponding to the decided refresh leveraging row driving unit to a don't care state; and internally generating the don't care lower row address of the refresh leveraging address to drive word lines according to a combined refresh leveraging address.