公开(公告)号：US20210028190A1

公开(公告)日：2021-01-28

申请号：US17028047

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won KIM ,  Kwang Young JUNG ,  Dong Seog EUN

IPC: H01L27/11582 ,  G11C11/4099 ,  H01L27/11526 ,  G11C7/14 ,  G11C16/10 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11565

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.

公开(公告)号：US20190326318A1

公开(公告)日：2019-10-24

申请号：US16242410

申请日：2019-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Young JUNG ,  Dong Won KIM

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L29/423

Abstract: A vertical-type memory device a vertical-type memory device comprising a substrate including a first region and a second region, adjacent to the first region, a first conductive layer extending on the first region and the second region, and a second conductive layer extending on the first region and the second region, the second conductive layer stacked on the first conductive layer. An upper surface of the substrate has a step portion at a boundary between the first region and the second region, and the upper surface of the substrate in the first region is lower than in the second region.

公开(公告)号：US20220139954A1

公开(公告)日：2022-05-05

申请号：US17575947

申请日：2022-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo-Heon KANG ,  Tae Hun KIM ,  Jae Ryong SIM ,  Kwang Young JUNG ,  Gi Yong CHUNG ,  Jee Hoon HAN ,  Doo Hee HWANG

IPC: H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.

公开(公告)号：US20200135761A1

公开(公告)日：2020-04-30

申请号：US16719089

申请日：2019-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won KIM ,  Kwang Young JUNG ,  Dong Seog EUN

IPC: H01L27/11582 ,  G11C16/10 ,  G11C7/14 ,  H01L27/11526 ,  G11C11/4099 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.