公开(公告)号：US20210028190A1

公开(公告)日：2021-01-28

申请号：US17028047

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won KIM ,  Kwang Young JUNG ,  Dong Seog EUN

IPC: H01L27/11582 ,  G11C11/4099 ,  H01L27/11526 ,  G11C7/14 ,  G11C16/10 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11565

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.

公开(公告)号：US20190035804A1

公开(公告)日：2019-01-31

申请号：US15938101

申请日：2018-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Won KIM ,  Hyun Goo JUN

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A vertical-type memory device and a manufacturing method thereof, the device including a substrate having a cell array region and a connection region; gate electrode layers stacked on the cell array region and the connection region of the substrate, the gate electrode layers forming a stepped structure in the connection region; a cell channel layer in the cell array region, the cell channel layer passing through the plurality of gate electrode layers; a dummy channel layer in the connection region, the dummy channel layer passing through at least one gate electrode layer of the plurality of gate electrode layers; a cell epitaxial layer disposed below the cell channel layer; and a dummy epitaxial layer disposed below the dummy channel layer, wherein the dummy epitaxial layer has a shape that is different from a shape of the cell epitaxial layer.

公开(公告)号：US20200135761A1

公开(公告)日：2020-04-30

申请号：US16719089

申请日：2019-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won KIM ,  Kwang Young JUNG ,  Dong Seog EUN

IPC: H01L27/11582 ,  G11C16/10 ,  G11C7/14 ,  H01L27/11526 ,  G11C11/4099 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.