公开(公告)号：US20230049110A1

公开(公告)日：2023-02-16

申请号：US17857379

申请日：2022-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changho Han ,  Mijeong Lim ,  Yuncheol Kim ,  Kwanghun Oh

IPC: G01R31/317 ,  G01R31/3177 ,  H01L21/66

Abstract: An integrated circuit includes first to nth metal layers vertically stacked on a substrate, and a test circuit outputting a test result signal according to a characteristic of each of the first to nth metal layers. The test circuit includes first to nth test circuits for generating a plurality of clock signals. Each clock signal of the plurality of clock signal has a frequency according to a characteristic of a corresponding metal layer among the first to nth metal layers, and n is a natural number.

公开(公告)号：US12000888B2

公开(公告)日：2024-06-04

申请号：US17857379

申请日：2022-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changho Han ,  Mijeong Lim ,  Yuncheol Kim ,  Kwanghun Oh

IPC: G01R31/317 ,  G01R31/30 ,  G01R31/3173 ,  G01R31/3177 ,  G01R31/3183 ,  G01R31/3185 ,  H01L21/66

CPC classification number: G01R31/31725 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/31727 ,  G01R31/3173 ,  G01R31/3177 ,  G01R31/318314 ,  H01L22/34 ,  G01R31/318513

Abstract: An integrated circuit includes first to nth metal layers vertically stacked on a substrate, and a test circuit outputting a test result signal according to a characteristic of each of the first to nth metal layers. The test circuit includes first to nth test circuits for generating a plurality of clock signals. Each clock signal of the plurality of clock signal has a frequency according to a characteristic of a corresponding metal layer among the first to nth metal layers, and n is a natural number.