公开(公告)号：US10095825B2

公开(公告)日：2018-10-09

申请号：US14843491

申请日：2015-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changho Han

IPC: G06F17/50

Abstract: There is provided a method of verifying a Fin-based integrated circuit layout in a layout verifying system. The method includes receiving a layout corresponding to a specific integrated circuit unit, extracting one or more device codes from the layout, and synthesizing a code stream using the one or more extracted device codes according to a gate line sequence. Each device code is based on a corresponding gate line unit in the layout that includes an active region, gate lines, and a number of intersecting points with silicon fins of the layout.

公开(公告)号：US12000888B2

公开(公告)日：2024-06-04

申请号：US17857379

申请日：2022-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changho Han ,  Mijeong Lim ,  Yuncheol Kim ,  Kwanghun Oh

IPC: G01R31/317 ,  G01R31/30 ,  G01R31/3173 ,  G01R31/3177 ,  G01R31/3183 ,  G01R31/3185 ,  H01L21/66

CPC classification number: G01R31/31725 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/31727 ,  G01R31/3173 ,  G01R31/3177 ,  G01R31/318314 ,  H01L22/34 ,  G01R31/318513

Abstract: An integrated circuit includes first to nth metal layers vertically stacked on a substrate, and a test circuit outputting a test result signal according to a characteristic of each of the first to nth metal layers. The test circuit includes first to nth test circuits for generating a plurality of clock signals. Each clock signal of the plurality of clock signal has a frequency according to a characteristic of a corresponding metal layer among the first to nth metal layers, and n is a natural number.

公开(公告)号：US20230049110A1

公开(公告)日：2023-02-16

申请号：US17857379

申请日：2022-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changho Han ,  Mijeong Lim ,  Yuncheol Kim ,  Kwanghun Oh

IPC: G01R31/317 ,  G01R31/3177 ,  H01L21/66

Abstract: An integrated circuit includes first to nth metal layers vertically stacked on a substrate, and a test circuit outputting a test result signal according to a characteristic of each of the first to nth metal layers. The test circuit includes first to nth test circuits for generating a plurality of clock signals. Each clock signal of the plurality of clock signal has a frequency according to a characteristic of a corresponding metal layer among the first to nth metal layers, and n is a natural number.

公开(公告)号：US09767248B2

公开(公告)日：2017-09-19

申请号：US14844420

申请日：2015-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejoong Song ,  Jung-Ho Do ,  Changho Han

IPC: G06F9/455 ,  G06F17/50 ,  G01R31/28

CPC classification number: G06F17/5081 ,  G01R31/2882 ,  G06F2217/14

Abstract: A semiconductor device and a layout verification method of a semiconductor device are provided. The layout verification method includes forming a plurality of standard cells each having a first type of a cross coupled structure (XC) and a second type of the XC on a substrate of the semiconductor device, forming a plurality of first inverters in which the first type of the XC is activated in the a plurality of the standard cells and a plurality of second inverters in which the second type of the XC is activated in the a plurality of the standard cells and estimating an electrical characteristic of the first type of the XC or the second type of the XC by measuring a magnitude of a signal delay of the plurality of the first inverters or the plurality of the second inverters.