公开(公告)号：US20230385497A1

公开(公告)日：2023-11-30

申请号：US18061636

申请日：2022-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Ok Kim ,  Jingon Lee ,  Mijeong Lim

IPC: G06F30/3315

CPC classification number: G06F30/3315 ,  G06F2119/12

Abstract: A method of designing a 3D integrated circuit includes generating a distance-delay table with respect to at least one of a first chip or a second chip stacked on the first chip, based on a thermal analysis result, calculating a first timing path distance with respect to a first timing path corresponding to the first chip in a 3D signal transfer path, calculating a second timing path distance with respect to a second timing path corresponding to the second chip in the 3D signal transfer path, calculating a 3D timing path distance by summing the first timing path distance and the second timing path distance, and setting a temperature margin with respect to a 3D timing path based on the distance-delay table and the 3D timing path distance.

公开(公告)号：US20230049110A1

公开(公告)日：2023-02-16

申请号：US17857379

申请日：2022-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changho Han ,  Mijeong Lim ,  Yuncheol Kim ,  Kwanghun Oh

IPC: G01R31/317 ,  G01R31/3177 ,  H01L21/66

Abstract: An integrated circuit includes first to nth metal layers vertically stacked on a substrate, and a test circuit outputting a test result signal according to a characteristic of each of the first to nth metal layers. The test circuit includes first to nth test circuits for generating a plurality of clock signals. Each clock signal of the plurality of clock signal has a frequency according to a characteristic of a corresponding metal layer among the first to nth metal layers, and n is a natural number.

公开(公告)号：US20240378363A1

公开(公告)日：2024-11-14

申请号：US18534390

申请日：2023-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Ok Kim ,  Yongjin Hong ,  Mijeong Lim

IPC: G06F30/3947

Abstract: An example embodiment provides a design method of an integrated circuit, including: placing a through-via; determining a keep-out zone around the through-via based on a saturated current variation rate according to a distance from the through-via; placing standard cells; determining a cell placed within the keep out zone among the cells; and setting a timing margin based on the distance from the through-via to the cell.

公开(公告)号：US12000888B2

公开(公告)日：2024-06-04

申请号：US17857379

申请日：2022-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changho Han ,  Mijeong Lim ,  Yuncheol Kim ,  Kwanghun Oh

IPC: G01R31/317 ,  G01R31/30 ,  G01R31/3173 ,  G01R31/3177 ,  G01R31/3183 ,  G01R31/3185 ,  H01L21/66

CPC classification number: G01R31/31725 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/31727 ,  G01R31/3173 ,  G01R31/3177 ,  G01R31/318314 ,  H01L22/34 ,  G01R31/318513

Abstract: An integrated circuit includes first to nth metal layers vertically stacked on a substrate, and a test circuit outputting a test result signal according to a characteristic of each of the first to nth metal layers. The test circuit includes first to nth test circuits for generating a plurality of clock signals. Each clock signal of the plurality of clock signal has a frequency according to a characteristic of a corresponding metal layer among the first to nth metal layers, and n is a natural number.