公开(公告)号：US20220207334A1

公开(公告)日：2022-06-30

申请号：US17459921

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suk Han LEE ,  Joo-Young KIM ,  Kyo Min SOHN ,  Ji Hoon KIM ,  Jae Hoon HEO

IPC: G06N3/063 ,  G11C11/412 ,  G11C11/419 ,  G11C11/54 ,  G11C11/418

Abstract: A neural network device including a convolution static random access memory (SRAM) configured to output a first operation value and a second operation value 1. An accumulation peripheral operator configured to perform an accumulation peripheral operation on the first and the second operation values, a multiplexer array configured to select and output an output value according to a selection signal, a diagonal accumulation SRAM configured to perform a bitwise accumulation of variable weight values and a spatial-wise accumulation operation on an input, a diagonal movement logic, and an addition array operator configured to perform an addition operation of output values of the diagonal movement logic subsequent to a shift operation, the multiplexer array selects any one of an output value of the accumulation peripheral operator and an output value of the addition array operator according to the selection signal and outputs the selected output value to the diagonal accumulation SRAM.

公开(公告)号：US20190206460A1

公开(公告)日：2019-07-04

申请号：US16032768

申请日：2018-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong IL O ,  Jun Hyung KIM ,  Kyo Min SOHN

IPC: G11C8/18 ,  G11C8/12 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4093 ,  G11C29/18

Abstract: A memory device can include a plurality of memory banks coupled to an input/output bus and a memory controller coupled to the plurality of memory banks. The memory controller can be configured to control operations of the plurality of memory banks, where each of the plurality of memory banks can include a bank array including a plurality of memory cells configured to store data, a latch circuit coupled to the input/output bus, where the latch circuit can be configured to store target data received via the input/output bus to provide stored target data, and a comparison circuit coupled to the latch circuit, where the comparison circuit can be configured to compare stored data output by the bank array with the stored target data to provide result data to the memory controller.