公开(公告)号：US20170186767A1

公开(公告)日：2017-06-29

申请号：US15224238

申请日：2016-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon BAEK ,  YOUNG WOO KIM ,  DONG SIK LEE ,  MIN YONG LEE ,  WOONG SEOP LEE

IPC: H01L27/115 ,  H01L23/522 ,  H01L29/06 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0649

Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.

公开(公告)号：US20190051664A1

公开(公告)日：2019-02-14

申请号：US16162720

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEOK CHEON BAEK ,  YOUNG WOO KIM ,  DONG SIK LEE ,  MIN YONG LEE ,  WOONG SEOP LEE

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11526 ,  H01L23/522 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/06

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0649

Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.