公开(公告)号：US20200043830A1

公开(公告)日：2020-02-06

申请号：US16388370

申请日：2019-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEOK CHEON BAEK

IPC: H01L23/48 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device includes a peripheral circuit area disposed on a first substrate and including circuit devices. A memory cell area is disposed on a second substrate and includes memory cells. A through wiring area includes a through contact plug and an insulating area. The through contact plug extends through the memory cell area and the second substrate and connects the memory cell area to the circuit devices. The insulating area surrounds the through contact plug. The insulating area includes a first insulating layer penetrating through the second substrate, a plurality of second insulating layers, a third insulating layer having a vertical extension portion, and a plurality of horizontal extension portions extended in parallel to a top surface of the second substrate from a side surface of the vertical extension portion to contact the second insulating layers.

公开(公告)号：US20190304992A1

公开(公告)日：2019-10-03

申请号：US16136474

申请日：2018-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEOK CHEON BAEK ,  BOH CHANG KIM ,  CHUNG KI MIN ,  JI HOON PARK ,  BYUNG KWAN YOU

IPC: H01L27/11582 ,  H01L29/423 ,  H01L23/00

Abstract: A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.

公开(公告)号：US20190051664A1

公开(公告)日：2019-02-14

申请号：US16162720

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEOK CHEON BAEK ,  YOUNG WOO KIM ,  DONG SIK LEE ,  MIN YONG LEE ,  WOONG SEOP LEE

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11526 ,  H01L23/522 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/06

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0649

Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.