公开(公告)号：US12073915B2

公开(公告)日：2024-08-27

申请号：US17888661

申请日：2022-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Min Hwi Kim ,  Ji-Sang Lee

IPC: G11C7/20 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/20 ,  G11C7/065 ,  G11C7/1039 ,  G11C7/12

Abstract: Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.

公开(公告)号：US12198782B2

公开(公告)日：2025-01-14

申请号：US18449864

申请日：2023-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Min Hwi Kim ,  Ji-Sang Lee

IPC: G11C7/20 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12

Abstract: Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.