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    Non-volatile memory device and programming method thereof
    1.
    发明授权
    Non-volatile memory device and programming method thereof 有权

    公开(公告)号：US12198764B2

    公开(公告)日：2025-01-14

    申请号：US18491966

    申请日：2023-10-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji-Sang Lee

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34 ,  G11C7/22 ,  G11C29/04

    Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.

    Memory device, operation method of memory device, and page buffer included in memory device
    2.
    发明授权
    Memory device, operation method of memory device, and page buffer included in memory device 有权

    公开(公告)号：US12073915B2

    公开(公告)日：2024-08-27

    申请号：US17888661

    申请日：2022-08-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung Cho ,  Min Hwi Kim ,  Ji-Sang Lee

    IPC: G11C7/20 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12

    CPC classification number: G11C7/20 ,  G11C7/065 ,  G11C7/1039 ,  G11C7/12

    Abstract: Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.

    Non-volatile memory device and programming method thereof
    4.
    发明授权
    Non-volatile memory device and programming method thereof 有权

    公开(公告)号：US10734078B2

    公开(公告)日：2020-08-04

    申请号：US16415274

    申请日：2019-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji-Sang Lee

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34 ,  G11C7/22 ,  G11C29/04

    Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.

    METHODS OF OPERATING NONVOLATILE MEMORY DEVICES THAT SUPPORT EFFICIENT ERROR DETECTION
    5.
    发明申请
    METHODS OF OPERATING NONVOLATILE MEMORY DEVICES THAT SUPPORT EFFICIENT ERROR DETECTION 审中-公开
    操作有效的错误检测的非易失性存储器件的操作方法

    公开(公告)号：US20150248930A1

    公开(公告)日：2015-09-03

    申请号：US14712939

    申请日：2015-05-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji-Sang Lee ,  Moosung Kim ,  Kihwan Choi

    IPC: G11C11/56 ,  G11C16/34

    CPC classification number: G11C11/5635 ,  G06F11/1048 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/02 ,  G11C16/0483 ,  G11C16/3413 ,  G11C16/3436 ,  G11C16/3454 ,  G11C29/04 ,  G11C2029/0411 ,  G11C2211/5621

    Abstract: Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells.

    Abstract translation: 操作非易失性存储器件的方法可以包括识别非易失性存储器件中的一个或多个多位非易失性存储器单元，其经历从擦除状态到至少部分编程状态的无意编程。 可以通过执行多个读取操作来生成错误检测数据，然后解码错误检测数据以识别具有错误的特定单元，来检测在编程第一多个多位非易失性存储器单元的操作期间产生的错误。 可以读取编程的第一多个多位非易失性存储单元和在编程操作期间被修改的强位数据向量，以支持错误检测。 然后可以将该数据连同从与第一多个多位非易失性存储器单元相关联的页面缓冲器读取的数据解码以识别第一多个多位非易失性存储器单元中的哪一个是无意编程的单元。

    Memory device, operation method of memory device, and page buffer included in memory device
    6.
    发明授权
    Memory device, operation method of memory device, and page buffer included in memory device 有权

    公开(公告)号：US12198782B2

    公开(公告)日：2025-01-14

    申请号：US18449864

    申请日：2023-08-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung Cho ,  Min Hwi Kim ,  Ji-Sang Lee

    IPC: G11C7/20 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12

    Abstract: Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.

    MEMORY SYSTEM AND OPERATING METHOD THEREOF
    7.
    发明公开
    MEMORY SYSTEM AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20240249782A1

    公开(公告)日：2024-07-25

    申请号：US18423047

    申请日：2024-01-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minkyeong CHOI ,  Joonsuc Jang ,  Ji-Sang Lee

    IPC: G11C16/34 ,  G11C16/04

    CPC classification number: G11C16/349 ,  G11C16/0483

    Abstract: A memory system includes: a memory device including a memory cell array and a control circuit; and a temperature sensor configured to measure a temperature of the memory device to generate a temperature value, wherein the control circuit is configured to: set a compensation sensing parameter based on the temperature value, determine a sensing parameter by applying the compensation sensing parameter to a basic sensing parameter corresponding to a read mode among a plurality of read modes having different read speeds, and read data from the memory cell array based on the sensing parameter.

    Nonvolatile memory device and a method of reading the same
    9.
    发明授权
    Nonvolatile memory device and a method of reading the same 有权

    公开(公告)号：US10210936B2

    公开(公告)日：2019-02-19

    申请号：US15398014

    申请日：2017-01-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun Jun Yoon ,  Ji-Sang Lee

    IPC: G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/20

    Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells, an address decoder configured to be connected to the memory cells through a plurality of word lines and to provide select or unselect read voltages to the word lines, and a control logic configured to control the address decoder to perform a plurality of read sequences in a continuous read mode and to adjust a word line setup start point in at least one of the read sequences to be different than a word line setup start point in at least one of the other read sequences, wherein the word line setup start point is a time at which the select or unselect read voltages begin to be provided to the word lines.

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