公开(公告)号：US20210158152A1

公开(公告)日：2021-05-27

申请号：US16906038

申请日：2020-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon MYUNG ,  Hyunjae Jang ,  In Huh ,  Hyeon Kyun Noh ,  Min-chul Park ,  Changwook Jeong

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/10

Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

公开(公告)号：US08901646B2

公开(公告)日：2014-12-02

申请号：US13727995

申请日：2012-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namho Jeon ,  Min-chul Park ,  Seunguk Han

IPC: H01L29/66 ,  G11C11/408 ,  H01L27/108 ,  H01L27/088 ,  H01L27/02

CPC classification number: H01L27/088 ,  G11C11/4085 ,  G11C11/4087 ,  H01L27/0207 ,  H01L27/10897

Abstract: A semiconductor device may include a substrate including an active region defined by a device isolation layer, gate electrodes extending in a first direction on the substrate and spaced apart from each other, gate tabs extending in a second direction different from the first direction and connecting adjacent gate electrodes to each other, the gate tabs spaced apart from each other, and a first contact plug disposed on the active region under a space confined by the adjacent gate electrodes and adjacent gate tabs. The space may include a first region having a first width and a second region having a second width smaller than the first width, the first contact plug may be disposed on the active region under the second region.

Abstract translation: 半导体器件可以包括：衬底，其包括由器件隔离层限定的有源区，沿着第一方向在衬底上延伸并且彼此间隔开的栅电极，栅极突片沿与第一方向不同的第二方向延伸并连接相邻 栅极彼此间隔开，栅极突片彼此间隔开;以及第一接触插塞，其设置在由相邻的栅电极和相邻的栅极接线片限定的空间之下的有源区域上。 空间可以包括具有第一宽度的第一区域和具有小于第一宽度的第二宽度的第二区域，第一接触插塞可以设置在第二区域下方的有源区域上。