公开(公告)号：US09564908B2

公开(公告)日：2017-02-07

申请号：US14955802

申请日：2015-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-young Song ,  Tae-ik Kim ,  Ji-hyun Kim

IPC: H03L7/06 ,  H03L7/081 ,  H03L7/099 ,  H03L7/095 ,  H03L7/08

CPC classification number: H03L7/0814 ,  H03L7/0802 ,  H03L7/081 ,  H03L7/087 ,  H03L7/095 ,  H03L7/099 ,  H03L7/0992 ,  H03L7/193 ,  H03L2207/06

Abstract: Provided are a digital phase-locked loop (DPLL) having improved signal characteristics, and a method of operating the DPLL. The DPLL includes a first tracking unit configured to receive a reference signal and a feedback signal that is generated by feeding back an output signal of the DPLL, track the feedback signal, and output a delayed reference signal, and a second tracking unit configured to receive a delayed feedback signal generated by delaying the feedback signal, and the delayed reference signal, and generate an output signal of the DPLL, of which a frequency is controlled according to a phase difference between the delayed feedback signal and the delayed reference signal.

Abstract translation: 提供了具有改进的信号特性的数字锁相环（DPLL）以及操作DPLL的方法。 DPLL包括：第一跟踪单元，被配置为接收参考信号和通过反馈DPLL的输出信号，跟踪反馈信号并输出​​延迟的参考信号而产生的反馈信号;以及第二跟踪单元，被配置为接收 通过延迟反馈信号产生的延迟反馈信号和延迟的参考信号，并产生DPLL的输出信号，其根据延迟的反馈信号和延迟的参考信号之间的相位差来控制频率。