公开(公告)号：US20240324182A1

公开(公告)日：2024-09-26

申请号：US18470537

申请日：2023-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongtak Cho ,  Inwoo Kim ,  Miso Myung ,  Jihun Lee

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/0335 ,  H10B12/315

Abstract: A semiconductor device includes a substrate that includes an active pattern, a bit line structure that crosses the active pattern, a storage node contact electrically connected to the active pattern next to the bit line structure, a spacer structure between a side surface of the bit line structure and the storage node contact, an upper surface of the spacer structure is at a vertical level lower than an upper surface of the bit line structure, an insulating pattern on the spacer structure, and a landing pad structure electrically connected to the storage node contact and on the spacer structure and the bit line structure. The landing pad structure include a first side surface in contact with the spacer structure, a second side surface in contact with the bit line structure, and a third side surface in contact with the insulating pattern.