公开(公告)号：US20240324182A1

公开(公告)日：2024-09-26

申请号：US18470537

申请日：2023-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongtak Cho ,  Inwoo Kim ,  Miso Myung ,  Jihun Lee

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/0335 ,  H10B12/315

Abstract: A semiconductor device includes a substrate that includes an active pattern, a bit line structure that crosses the active pattern, a storage node contact electrically connected to the active pattern next to the bit line structure, a spacer structure between a side surface of the bit line structure and the storage node contact, an upper surface of the spacer structure is at a vertical level lower than an upper surface of the bit line structure, an insulating pattern on the spacer structure, and a landing pad structure electrically connected to the storage node contact and on the spacer structure and the bit line structure. The landing pad structure include a first side surface in contact with the spacer structure, a second side surface in contact with the bit line structure, and a third side surface in contact with the insulating pattern.

公开(公告)号：US20240414909A1

公开(公告)日：2024-12-12

申请号：US18442363

申请日：2024-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyun Park ,  Inwoo Kim ,  Jihun Lee ,  Seongtak Cho

IPC: H10B12/00 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes an active pattern on a substrate; a gate structure extending through an upper portion of the active pattern; a bit line structure on a central portion of the active pattern; a lower contact plug on each of opposite end portions of the active pattern; and an upper contact plug structure on the lower contact plug. The upper contact plug structure includes a first upper contact plug and a second upper contact plug on the first upper contact plug. The second upper contact plug contacts the first upper contact plug. The first upper contact plug includes a first metal pattern and a barrier pattern covering a lower surface and a sidewall of the first metal pattern. An upper surface of the bit line structure contacts a lower surface of the second upper contact plug and does not contact the barrier pattern.