公开(公告)号：US20240224522A1

公开(公告)日：2024-07-04

申请号：US18475070

申请日：2023-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Homoon SHIN ,  Jonghoon PARK ,  Juyoung YANG ,  Jungseok HWANG ,  Sunghoon KIM ,  Pansuk KWAK ,  Ahreum KIM ,  Myunghun LEE ,  Changyeon YU ,  Mookyu BAE ,  Sungun LEE

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A non-volatile memory device may include a memory cell region and a peripheral circuit region positioned below the memory cell region in the vertical direction. The memory cell region may include a plurality of channel structures extending in a vertical direction, a first metal layer over the plurality of channel structures, a first capping layer over the first metal layer, a first upper insulation layer over the first capping layer, and at least one first dummy contact penetrating through the first capping layer. The first metal layer may include a plurality of bit lines and at least one dummy bit line. The bit lines may be respectively connected to the plurality of channel structures. The at least one first dummy contact may be on the at least one dummy bit line and may provide a migration path for hydrogen ions in the first upper insulation layer.