公开(公告)号：US20220399273A1

公开(公告)日：2022-12-15

申请号：US17721481

申请日：2022-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyeon YU ,  Pansuk KWAK ,  Daeseok BYEON

IPC: H01L23/528 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/11573

Abstract: A vertical memory device may include a first conductive line structure and an address decoder. The first conductive line structure may be on a substrate. The first conductive line structure may include conductive lines and insulation layers alternately and repeatedly stacked in a direction perpendicular to the substrate. The address decoder may be connected to a first end of each of conductive lines included in the first conductive line structure. The address decoder may apply electrical signal to the conductive lines. In each of the conductive lines, a first portion adjacent to the first end and a second portion adjacent to a second end may have different shapes. A first resistance in the first portion may be lower than a second resistance in the second portion. RC delay of the conductive lines may be reduced.

公开(公告)号：US20230041064A1

公开(公告)日：2023-02-09

申请号：US17709910

申请日：2022-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyeon YU ,  Pansuk KWAK ,  Daeseok BYEON

IPC: G11C16/04 ,  G11C16/08

Abstract: A semiconductor device includes a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including select transistors and memory cells; pass transistors configured to provide select signals to select lines connected to a selected memory block; and ground transistors configured to supply a first voltage to select lines connected to unselected memory blocks. The ground transistors include at least one common gate structure, at least one common active region, and individual active regions, and each of the common gate structure and the common active region are shared by two or more ground transistors, among the ground transistors. The common gate structure is between the common active region and the individual active regions, and includes a first region extending in a first direction and a second region extending in a second direction, intersecting the first direction.

公开(公告)号：US20240170067A1

公开(公告)日：2024-05-23

申请号：US18388956

申请日：2023-11-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanmin NAM ,  Jeunghwan PARK ,  Changyeon YU

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/24

CPC classification number: G11C16/08 ,  G11C16/0433 ,  G11C16/24

Abstract: A semiconductor device includes word lines disposed on a substrate and spaced apart in a first direction perpendicular to an upper surface of the substrate, a string select line disposed on the word lines, memory strings extending in the first direction on the substrate, each memory string including a first channel extending in the first direction through the word lines, and memory cells constituted by the word lines around the first channel, bit lines electrically connected to the memory strings, and a strapping line connected to the string select.

公开(公告)号：US20240224522A1

公开(公告)日：2024-07-04

申请号：US18475070

申请日：2023-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Homoon SHIN ,  Jonghoon PARK ,  Juyoung YANG ,  Jungseok HWANG ,  Sunghoon KIM ,  Pansuk KWAK ,  Ahreum KIM ,  Myunghun LEE ,  Changyeon YU ,  Mookyu BAE ,  Sungun LEE

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A non-volatile memory device may include a memory cell region and a peripheral circuit region positioned below the memory cell region in the vertical direction. The memory cell region may include a plurality of channel structures extending in a vertical direction, a first metal layer over the plurality of channel structures, a first capping layer over the first metal layer, a first upper insulation layer over the first capping layer, and at least one first dummy contact penetrating through the first capping layer. The first metal layer may include a plurality of bit lines and at least one dummy bit line. The bit lines may be respectively connected to the plurality of channel structures. The at least one first dummy contact may be on the at least one dummy bit line and may provide a migration path for hydrogen ions in the first upper insulation layer.

公开(公告)号：US20230073878A1

公开(公告)日：2023-03-09

申请号：US17886194

申请日：2022-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyeon YU ,  Pansuk KWAK ,  Daeseok BYEON

IPC: H03K19/00 ,  H03K19/003 ,  G06F1/26 ,  H03K3/027 ,  H03K17/687

Abstract: An integrated circuit includes a logic circuit comprising a plurality of logic transistors, the logic circuit comprising a plurality of logic gate lines extending in a first direction; and a power gating circuit comprising a plurality of power gating transistors, the power gating circuit comprising a first power gate line extending in a second direction that is perpendicular to the first direction, and the power gating circuit being connected to the logic circuit, wherein a plurality of source regions respectively included in the plurality of power gating transistors are connected to each other, or a plurality of drain regions respectively included in the plurality of power gating transistors are connected to each other.