-
1.
公开(公告)号:US20200151053A1
公开(公告)日:2020-05-14
申请号:US16384319
申请日:2019-04-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sang-Uhn CHA , Nam-Sung KIM , Kyo-Min SOHN
Abstract: Semiconductor memory device includes a memory cell array and an interface circuit including an ECC engine. The memory cell array includes a normal cell region and a parity cell region including a first sub parity region and a second sub parity region. The interface circuit receives main data and sub data comprising external parity or a data mask signal, generates a flag signal based on mask bits of the data mask signal, performs ECC encoding operation on the main data in response to an operation mode and the flag signal, stores the main data in the normal cell region, stores either the external parity or the flag signal in the second sub parity region in response to the operation mode, performs an ECC decoding operation on the main data read from the normal cell region in response to the operation mode and the flag signal.
-
公开(公告)号:US20140325248A1
公开(公告)日:2014-10-30
申请号:US14263309
申请日:2014-04-28
Inventor: Ho-Young KIM , Nam-Sung KIM , Daniel W. CHANG
IPC: G06F1/32
CPC classification number: G06F1/3234 , G06F13/4234 , Y02D10/14 , Y02D10/151
Abstract: A method for adjusting bandwidth, a bandwidth scaler and an apparatus are provided. The method for adjusting bandwidth involves determining a dynamic context of a processor, and based on the determined dynamic context, scaling bandwidth between the processor and a memory.
Abstract translation: 提供了一种用于调整带宽的方法,带宽缩放器和装置。 用于调整带宽的方法涉及确定处理器的动态上下文,并且基于所确定的动态上下文,缩放处理器和存储器之间的带宽。
-