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    PHASE-LOCKED LOOP CIRCUIT INCLUDING A PLURALITY OF CAPACITOR CELL ARRAYS WITH DIFFERENT CAPACITANCE CHANGES AND CONTROL METHOD THEREOF
    1.
    发明申请
    PHASE-LOCKED LOOP CIRCUIT INCLUDING A PLURALITY OF CAPACITOR CELL ARRAYS WITH DIFFERENT CAPACITANCE CHANGES AND CONTROL METHOD THEREOF 有权

    公开(公告)号：US20250132764A1

    公开(公告)日：2025-04-24

    申请号：US18884601

    申请日：2024-09-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Pillseong KANG ,  Chulho KIM ,  Sangmin YOO ,  Sangho LEE ,  Joonhee LEE ,  Ikkyun JO

    IPC: H03L7/099 ,  H03B5/12

    Abstract: A phase-locked loop (PLL) circuit comprising an oscillator including a first and a second capacitor cell array, each including a plurality of capacitor cells, and a control logic circuit connected to the oscillator. The control logic circuit configured to generate control code configured to control the oscillator such that the oscillator is configured to output a signal with a target frequency, the control code generated based on a first frequency of a first signal output from the oscillator and the target frequency, control at least some of capacitor cells included in the first capacitor cell array based on a first partial code generated based on a specified number of bits of the control code, and control at least some of capacitor cells included in the second capacitor cell array based on a second partial code generated based on bits other than the specified number of bits of the control code.

    PHASE-LOCKED LOOP CIRCUIT INCLUDING A PLURALITY OF CAPACITOR CELLS AND METHOD OF CONTROLLING THE SAME
    2.
    发明申请
    PHASE-LOCKED LOOP CIRCUIT INCLUDING A PLURALITY OF CAPACITOR CELLS AND METHOD OF CONTROLLING THE SAME 有权

    公开(公告)号：US20250080124A1

    公开(公告)日：2025-03-06

    申请号：US18809865

    申请日：2024-08-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Pillseong KANG ,  Chulho KIM ,  Sangho LEE ,  Joonhee LEE ,  Ikkyun JO

    IPC: H03L7/099 ,  H03L7/093

    Abstract: A phase-locked loop circuit includes an oscillator including a plurality of capacitor cells, and a control logic circuit that receives an output from the oscillator. The control logic circuit compares a target frequency with a first frequency of a first signal output from the oscillator, generates a first input code to control at least a portion of the plurality of capacitor cells to output a signal having the target frequency based on the comparison, generates a first output code corresponding to the first input code when the first input code is within a predetermined range of input codes, and controls at least two capacitor cells from among the plurality of capacitor cells based on the first output code. The oscillator may output a second signal having a second frequency through an electrical path including capacitor cells other than grounded capacitor cells from among the plurality of capacitor cells.

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