公开(公告)号：US20230022545A1

公开(公告)日：2023-01-26

申请号：US17680507

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： EUI BOK LEE ,  WANDON KIM ,  RAKHWAN KIM

IPC: H01L23/522 ,  H01L29/417 ,  H01L21/768

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The device includes an FEOL layer, which includes a plurality of individual devices, on a substrate, and first, second, and third metal layers sequentially stacked on the FEOL layer. The second metal layer includes an interlayer insulating layer and an interconnection line in the interlayer insulating layer. The interconnection line includes a lower via portion electrically connected to the first metal layer, an upper via portion electrically connected to the third metal layer, and a line portion between the lower via portion and the upper via portion. A line width of an upper portion of the interconnection line gradually decreases in a vertical direction away from the substrate, and a line width of a lower portion of the interconnection line gradually increases in a vertical direction away from the substrate.

公开(公告)号：US20220208673A1

公开(公告)日：2022-06-30

申请号：US17344670

申请日：2021-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUI BOK LEE ,  RAKHWAN KIM ,  WANDON KIM ,  SEOWOO NAM ,  SUNYOUNG NOH ,  KI CHUL PARK ,  JONGCHAN SHIN ,  MINJOO LEE ,  HYUNBAE LEE ,  SEUNGSEOK HA

IPC: H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L27/088

Abstract: Disclosed is a semiconductor device including a substrate, a first interlayer dielectric layer on the substrate, a plurality of first vias in the first interlayer dielectric layer, a second interlayer dielectric layer on the first interlayer dielectric layer, and a first power line and a first lower line in the second interlayer dielectric layer that are electrically connected to respective ones of the first vias. A first width in a first direction of the first power line is greater than a second width in the first direction of the first lower line. The first power line includes a first metallic material. The first lower line includes a second metallic material. The first vias includes a third metallic material. The first, second, and third metallic materials are different from each other.

公开(公告)号：US20220068805A1

公开(公告)日：2022-03-03

申请号：US17235984

申请日：2021-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGJIN LEE ,  KYUNGWOOK KIM ,  RAKHWAN KIM ,  SEUNGYONG YOO ,  EUN-JI JUNG

IPC: H01L23/522 ,  H01L23/532 ,  H01L29/45

Abstract: Semiconductor devices includes a first interlayer insulating layer, a lower interconnection line in the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through the etch stop layer and contacting the lower interconnection line. The via portion includes a barrier pattern and a conductive pattern. The barrier pattern includes a first barrier layer between the conductive pattern and the second interlayer insulating layer, and a second barrier layer between the conductive pattern and the lower interconnection line. A resistivity of the first barrier layer is greater than that of the second barrier layer. A nitrogen concentration of the first barrier layer is greater than that of the second barrier layer.