公开(公告)号：US20220246477A1

公开(公告)日：2022-08-04

申请号：US17405134

申请日：2021-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGCHAN SHIN ,  CHANGMIN PARK

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/308

Abstract: A semiconductor device includes; a substrate including a first region and a second region adjacent to the first region in a first direction, a pair of active patterns adjacently disposed on the substrate, wherein the pair of active patterns includes a first active pattern extending in the first direction and a second active pattern extending in parallel with the first active pattern, a first gate electrode on the first region and extending in a second direction that intersect the first direction across the first active pattern and the second active pattern, and a second gate electrode on the second region and extending in the second direction across the first active pattern and the second active pattern. A width of the first active pattern is greater on the first region than on the second region, a width of the second active pattern is greater on the first region than on the second region, and an interval between the first active pattern and the second active pattern is constant from the first region to the second region.

公开(公告)号：US20190311902A1

公开(公告)日：2019-10-10

申请号：US16185137

申请日：2018-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGCHAN SHIN

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/528

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises sequentially forming a target layer and a first mask layer on a substrate, patterning the first mask layer to form a first opening in the first mask layer, forming a spacer covering an inner wall of the first opening, forming on the first mask layer a first photoresist pattern having a second opening vertically overlapping at least a portion of the spacer, forming a third opening in the first mask layer that is adjacent to the first opening by using the spacer as a mask to remove a portion of the first mask layer that is exposed to the second opening, and using the first mask layer and the spacer as a mask to pattern the target layer.

公开(公告)号：US20230274980A1

公开(公告)日：2023-08-31

申请号：US18134858

申请日：2023-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGCHAN SHIN ,  CHANGMIN PARK

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/308

CPC classification number: H01L21/8234 ,  H01L27/088 ,  H01L21/3086

Abstract: A semiconductor device includes; a substrate including a first region and a second region adjacent to the first region in a first direction, a pair of active patterns adjacently disposed on the substrate, wherein the pair of active patterns includes a first active pattern extending in the first direction and a second active pattern extending in parallel with the first active pattern, a first gate electrode on the first region and extending in a second direction that intersect the first direction across the first active pattern and the second active pattern, and a second gate electrode on the second region and extending in the second direction across the first active pattern and the second active pattern. A width of the first active pattern is greater on the first region than on the second region, a width of the second active pattern is greater on the first region than on the second region, and an interval between the first active pattern and the second active pattern is constant from the first region to the second region.

公开(公告)号：US20220208673A1

公开(公告)日：2022-06-30

申请号：US17344670

申请日：2021-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUI BOK LEE ,  RAKHWAN KIM ,  WANDON KIM ,  SEOWOO NAM ,  SUNYOUNG NOH ,  KI CHUL PARK ,  JONGCHAN SHIN ,  MINJOO LEE ,  HYUNBAE LEE ,  SEUNGSEOK HA

IPC: H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L27/088

Abstract: Disclosed is a semiconductor device including a substrate, a first interlayer dielectric layer on the substrate, a plurality of first vias in the first interlayer dielectric layer, a second interlayer dielectric layer on the first interlayer dielectric layer, and a first power line and a first lower line in the second interlayer dielectric layer that are electrically connected to respective ones of the first vias. A first width in a first direction of the first power line is greater than a second width in the first direction of the first lower line. The first power line includes a first metallic material. The first lower line includes a second metallic material. The first vias includes a third metallic material. The first, second, and third metallic materials are different from each other.