公开(公告)号：US20240258239A1

公开(公告)日：2024-08-01

申请号：US18427795

申请日：2024-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGBONG LEE ,  Seowoo Nam ,  SUNGHO SEO ,  SEOKMYEONG KANG ,  KyuHoon Choi ,  SEUNGSEOK HA

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76832 ,  H01L21/76895

Abstract: A semiconductor device includes: a first interlayer insulating layer disposed on a substrate; a first conductive line disposed in the first interlayer insulating layer and having a protrusion protruding above an upper side of the first interlayer insulating layer; an etch stop layer disposed on the first interlayer insulating layer and the first conductive line; and a via passing through the etch stop layer and contacting the first conductive line, wherein the etch stop layer includes a first etch stop layer having a curved shape in a cross-sectional view and a second etch stop layer disposed on the first etch stop layer and having a thickness variation.

公开(公告)号：US20220208673A1

公开(公告)日：2022-06-30

申请号：US17344670

申请日：2021-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUI BOK LEE ,  RAKHWAN KIM ,  WANDON KIM ,  SEOWOO NAM ,  SUNYOUNG NOH ,  KI CHUL PARK ,  JONGCHAN SHIN ,  MINJOO LEE ,  HYUNBAE LEE ,  SEUNGSEOK HA

IPC: H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L27/088

Abstract: Disclosed is a semiconductor device including a substrate, a first interlayer dielectric layer on the substrate, a plurality of first vias in the first interlayer dielectric layer, a second interlayer dielectric layer on the first interlayer dielectric layer, and a first power line and a first lower line in the second interlayer dielectric layer that are electrically connected to respective ones of the first vias. A first width in a first direction of the first power line is greater than a second width in the first direction of the first lower line. The first power line includes a first metallic material. The first lower line includes a second metallic material. The first vias includes a third metallic material. The first, second, and third metallic materials are different from each other.

公开(公告)号：US20190312145A1

公开(公告)日：2019-10-10

申请号：US16437056

申请日：2019-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： DAEWON HA ,  SEUNGSEOK HA ,  BYOUNG HAK HONG

IPC: H01L29/78 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin.

公开(公告)号：US20180040699A1

公开(公告)日：2018-02-08

申请号：US15463187

申请日：2017-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： DAEWON HA ,  SEUNGSEOK HA ,  BYOUNG HAK HONG

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin.