公开(公告)号：US20210057011A1

公开(公告)日：2021-02-25

申请号：US16847741

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan HATCHER ,  Titash RAKSHIT ,  Jorge KITTL ,  Joon Goo HONG ,  Dharmendar PALLE

IPC: G11C11/16 ,  G06F17/17 ,  G06F17/16

Abstract: A method, system and electronic device for mitigating variance in a two transistor two resistive memory element (2T2R) circuit is provided. The method includes calculating a sum of a number of logical 1's in a column of bitcells in the 2T2R circuit, N, of an input vector, sensing output current values from each current line in the column of bitcells and calculating an inner product, M, of the input vector and the bitcells in the column in the 2T2R circuit based on the sensed output current values