公开(公告)号：US20210057011A1

公开(公告)日：2021-02-25

申请号：US16847741

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan HATCHER ,  Titash RAKSHIT ,  Jorge KITTL ,  Joon Goo HONG ,  Dharmendar PALLE

IPC: G11C11/16 ,  G06F17/17 ,  G06F17/16

Abstract: A method, system and electronic device for mitigating variance in a two transistor two resistive memory element (2T2R) circuit is provided. The method includes calculating a sum of a number of logical 1's in a column of bitcells in the 2T2R circuit, N, of an input vector, sensing output current values from each current line in the column of bitcells and calculating an inner product, M, of the input vector and the bitcells in the column in the 2T2R circuit based on the sensed output current values

公开(公告)号：US20200279176A1

公开(公告)日：2020-09-03

申请号：US16448842

申请日：2019-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. HATCHER ,  Titash RAKSHIT ,  Jorge KITTL ,  Rwik SENGUPTA ,  Dharmendar PALLE ,  Joon Goo HONG

IPC: G06N5/04 ,  G11C11/16 ,  G11C13/00 ,  G11C11/22 ,  G06F17/16

Abstract: A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET being connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, a third FET and a third resistive memory element connected to a drain of the third FET, and a fourth FET and a fourth resistive memory element connected to a drain of the fourth FET, the drain of the third FET is connected to a gate of the fourth FET and the drain of the fourth FET being connected to a gate of the third FET.

公开(公告)号：US20170110595A1

公开(公告)日：2017-04-20

申请号：US15149722

申请日：2016-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Stephen RODDER ,  Joon Goo HONG ,  Titash RAKSHIT

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/778 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684

Abstract: A Gate-All-Around (GAA) Field Effect Transistor (FET) can include a horizontal nanosheet conductive channel structure having a width in a horizontal direction in the GAA FET, a height that is perpendicular to the horizontal direction, and a length that extends in the horizontal direction, where the width of the horizontal nanosheet conductive channel structure defines a physical channel width of the GAA FET. First and second source/drain regions can be located at opposing ends of the horizontal nanosheet conductive channel structure and a unitary gate material completely surrounding the horizontal nanosheet conductive channel structure.