公开(公告)号：US20240234325A1

公开(公告)日：2024-07-11

申请号：US18239846

申请日：2023-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： JOONGHYUN BAEK ,  HYUNSOO CHUNG ,  SEOK-HONG KWON

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/5383 ,  H01L23/49811 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/105 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package includes a first redistribution layer, a first semiconductor chip, and a second semiconductor chip. The first redistribution layer includes a first intervening interconnection layer and a first upper interconnection layer. The first intervening interconnection layer includes a first intervening insulating layer, a first intervening redistribution pattern, and a stress buffer pattern, which is spaced apart from the first intervening redistribution pattern and is in an electrically floated state. The first upper interconnection layer includes a first upper insulating layer, a first upper redistribution pattern, and a first test pad on the first upper redistribution pattern. An area of the stress buffer pattern is larger than an area of the first test pad.