公开(公告)号：US11222894B2

公开(公告)日：2022-01-11

申请号：US17032425

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Youn Kim ,  Sang Jung Kang ,  Ji Su Kang ,  Yun Sang Shin

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/12 ,  H01L29/49 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/786 ,  H01L21/762 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including NMOS and PMOS regions; first and second active patterns on the NMOS region; third and fourth active patterns on the PMOS region, the third active pattern being spaced apart from the first active pattern; a first dummy gate structure on the first and third active patterns; a second dummy gate structure on the second and fourth active patterns; a normal gate structure on the third active pattern; a first source/drain pattern on the third active pattern and between the normal gate structure and the first dummy gate structure; and a first element separation structure between the first and second dummy gate structures and separating the third and fourth active patterns, wherein the first dummy gate structure includes a first dummy insulation gate intersecting the third active pattern.

公开(公告)号：US11476341B2

公开(公告)日：2022-10-18

申请号：US17105868

申请日：2020-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Youn Kim ,  Sang Jung Kang ,  Jin Woo Kim ,  Seul Gi Yun

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/786

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first region and a second region, a first gate structure extending in a first direction on the first region of the substrate, the first gate structure including a first gate insulation film and a first work function film disposed on the first gate insulation film, and a second gate structure extending in the first direction on the second region of the substrate, the second gate structure including a second gate insulation film and a second work function film disposed on the second gate insulation film, wherein a first thickness of the first work function film in a second direction intersecting the first direction is different from a second thickness of the second work function film in the second direction, and wherein a first height of the first work function film in a third direction perpendicular to the first and second directions is different from a second height of the second work function film in the third direction.

公开(公告)号：US11462613B2

公开(公告)日：2022-10-04

申请号：US17032261

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Youn Kim ,  Sang Jung Kang ,  Ji Su Kang ,  Yun Sang Shin

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8238

Abstract: A semiconductor device includes first to sixth active patterns extending in a first direction and spaced apart in the first direction and a second direction; a field insulating layer between the first and second active patterns, an upper surface thereof being lower than upper surfaces of the first and second active patterns; a first gate structure on the field insulating layer and the first active pattern and extending in the second direction; a second gate structure on the field insulating layer and the second active pattern and extending in the second direction; a first separation trench extending between the second and third active patterns and the fifth and sixth active patterns, and a second separation trench extending between the first and second gate structures, wherein a lowest surface of the first separation trench is higher than a lowest surface of the second separation trench.

公开(公告)号：US11569237B2

公开(公告)日：2023-01-31

申请号：US17569950

申请日：2022-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Youn Kim ,  Sang Jung Kang ,  Ji Su Kang ,  Yun Sang Shin

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/786 ,  H01L29/66 ,  H01L21/762 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including NMOS and PMOS regions; first and second active patterns on the NMOS region; third and fourth active patterns on the PMOS region, the third active pattern being spaced apart from the first active pattern; a first dummy gate structure on the first and third active patterns; a second dummy gate structure on the second and fourth active patterns; a normal gate structure on the third active pattern; a first source/drain pattern on the third active pattern and between the normal gate structure and the first dummy gate structure; and a first element separation structure between the first and second dummy gate structures and separating the third and fourth active patterns, wherein the first dummy gate structure includes a first dummy insulation gate intersecting the third active pattern.