公开(公告)号：US11222894B2

公开(公告)日：2022-01-11

申请号：US17032425

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Youn Kim ,  Sang Jung Kang ,  Ji Su Kang ,  Yun Sang Shin

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/12 ,  H01L29/49 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/786 ,  H01L21/762 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including NMOS and PMOS regions; first and second active patterns on the NMOS region; third and fourth active patterns on the PMOS region, the third active pattern being spaced apart from the first active pattern; a first dummy gate structure on the first and third active patterns; a second dummy gate structure on the second and fourth active patterns; a normal gate structure on the third active pattern; a first source/drain pattern on the third active pattern and between the normal gate structure and the first dummy gate structure; and a first element separation structure between the first and second dummy gate structures and separating the third and fourth active patterns, wherein the first dummy gate structure includes a first dummy insulation gate intersecting the third active pattern.

公开(公告)号：US11011519B2

公开(公告)日：2021-05-18

申请号：US16368990

申请日：2019-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eui Chul Hwang ,  Ju Youn Kim ,  Hyung Joo Na ,  Bong Seok Suh ,  Sang Min Yoo ,  Joo Ho Jung ,  Sung Moon Lee

IPC: H01L27/092 ,  H01L27/02 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66

Abstract: A semiconductor device and a method for fabricating the same, the device including an active pattern extending in a first direction on a substrate; a field insulating film surrounding a part of the active pattern; a first gate structure extending in a second direction on the active pattern and the field insulating film, a second gate structure spaced apart from the first gate structure and extending in the second direction on the active pattern and the field insulating film; and a first device isolation film between the first and second gate structure, wherein a side wall of the first gate structure facing the first device isolation film includes an inclined surface having an acute angle with respect to an upper surface of the active pattern, and a lowermost surface of the first device isolation film is lower than or substantially coplanar with an uppermost surface of the field insulating film.

公开(公告)号：US10978570B2

公开(公告)日：2021-04-13

申请号：US16050652

申请日：2018-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Youn Kim ,  Se Ki Hong

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L27/108 ,  H01L21/28 ,  H01L27/11

Abstract: A semiconductor device includes a substrate with first and second areas, a first trench in the first area, and first and second PMOS transistors in the first area and the second area, respectively. The first transistor includes a first gate insulating layer, a first TiN layer on and contacting the first gate insulating layer, and a first gate electrode on and contacting the first TiN layer. The second transistor includes a second gate insulating layer, a second TiN layer on and contacting the second gate insulating layer, and a first TiAlC layer on and contacting the second TiN layer. The first gate insulating layer, the first TiN layer, and the first gate electrode are within the first trench. The first gate electrode does not include aluminum. A threshold voltage of the first transistor is smaller than a threshold voltage of the second transistor.

公开(公告)号：US10431673B2

公开(公告)日：2019-10-01

申请号：US15842050

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Youn Kim

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/165

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, source/drain regions on the fin, a recess between the source/drain regions, a device isolation region including a capping layer extending along an inner surface of the recess and a device isolating layer on the capping layer to fill the recess, a dummy gate structure on the device isolation region and including a dummy gate insulating layer, outer spacers on opposite sidewalls of the dummy gate structure, first inner spacers between the dummy gate structure and the outer spacers, and a second inner spacer between the device isolation region and the dummy gate insulating layer.

公开(公告)号：US10068901B2

公开(公告)日：2018-09-04

申请号：US15413680

申请日：2017-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Youn Kim ,  Gi Gwan Park

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device including a substrate includes a first region and a second region and first and second transistors in the first and second regions, respectively. The first transistor includes a first gate insulating layer on the substrate, a first lower TiN layer on and in contact with the first gate insulating layer, a first etch-stop layer on the first lower TiN layer and a first upper gate electrode on the first etch-stop layer. The second transistor includes a second gate insulating layer on the substrate, a second lower TiN layer on and in contact with the second gate insulating layer, a second etch-stop layer on the second lower TiN layer and a second upper gate electrode on the second etch-stop layer. A thickness of the first lower TiN layer is less than a thickness of the second lower TiN layer.

公开(公告)号：US12183734B2

公开(公告)日：2024-12-31

申请号：US18230052

申请日：2023-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Min Yoo ,  Ju Youn Kim ,  Hyung Joo Na ,  Bong Seok Suh ,  Joo Ho Jung ,  Eui Chul Hwang ,  Sung Moon Lee

IPC: H01L27/088 ,  H01L21/762 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.

公开(公告)号：US11569237B2

公开(公告)日：2023-01-31

申请号：US17569950

申请日：2022-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Youn Kim ,  Sang Jung Kang ,  Ji Su Kang ,  Yun Sang Shin

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/786 ,  H01L29/66 ,  H01L21/762 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including NMOS and PMOS regions; first and second active patterns on the NMOS region; third and fourth active patterns on the PMOS region, the third active pattern being spaced apart from the first active pattern; a first dummy gate structure on the first and third active patterns; a second dummy gate structure on the second and fourth active patterns; a normal gate structure on the third active pattern; a first source/drain pattern on the third active pattern and between the normal gate structure and the first dummy gate structure; and a first element separation structure between the first and second dummy gate structures and separating the third and fourth active patterns, wherein the first dummy gate structure includes a first dummy insulation gate intersecting the third active pattern.

公开(公告)号：US11538807B2

公开(公告)日：2022-12-27

申请号：US17318133

申请日：2021-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eui Chul Hwang ,  Ju Youn Kim ,  Hyung Joo Na ,  Bong Seok Suh ,  Sang Min Yoo ,  Joo Ho Jung ,  Sung Moon Lee

IPC: H01L27/092 ,  H01L27/02 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66

Abstract: A semiconductor device and a method for fabricating the same, the device including an active pattern extending in a first direction on a substrate; a field insulating film surrounding a part of the active pattern; a first gate structure extending in a second direction on the active pattern and the field insulating film, a second gate structure spaced apart from the first gate structure and extending in the second direction on the active pattern and the field insulating film; and a first device isolation film between the first and second gate structure, wherein a side wall of the first gate structure facing the first device isolation film includes an inclined surface having an acute angle with respect to an upper surface of the active pattern, and a lowermost surface of the first device isolation film is lower than or substantially coplanar with an uppermost surface of the field insulating film.

公开(公告)号：US20190393220A1

公开(公告)日：2019-12-26

申请号：US16204095

申请日：2018-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung Joo Na ,  Ju Youn Kim ,  Bong Seok Suh ,  Sang Min Yoo ,  Joo Ho Jung ,  Eui Chul Hwang ,  Sung Moon Lee

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/033

Abstract: A FINFET includes a first fin extending in a first direction on a substrate and, a second fin extending in the first direction and spaced apart from the first fin in the first direction. A third fin is provided with a long side shorter than long sides of the first fin and the second fin and is disposed between the first fin and the second fin. A first gate structure extends in a second direction different from the first direction and crosses the first fin. A device isolation layer is disposed on a lower sidewall of each of the first, second and third fins and is formed to extend in the first direction. An electrically insulating diffusion break region includes a first portion crossing between the first fin and the third fin, a second portion crossing between the second fin and the third fin, and a third portion disposed between the first portion and the second portion on the third fin. The diffusion break region extends in the second direction on the device isolation layer. A level of a lower surface of the third portion is higher than a level of a lower end of each of the first portion and the second portion and is lower than a level of an upper surface of the first gate structure.

公开(公告)号：US10431583B2

公开(公告)日：2019-10-01

申请号：US15430265

申请日：2017-02-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Youn Kim ,  Gi Gwan Park

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first region and a second region. First and second dielectric films are positioned above the substrate in the first region and the second region, respectively. First and second gate stacks are disposed on the first and second dielectric films, respectively. The first gate stack includes a first TiAlC film in direct contact with the first dielectric film, and a first barrier film and a first metal film sequentially stacked on the first TiAlC film. The second gate stack includes a first LaO film in direct contact with the second dielectric film. A second TiAlC film, a second barrier film, and a second metal film are sequentially stacked on the first LaO film.