公开(公告)号：US20170133367A1

公开(公告)日：2017-05-11

申请号：US15416016

申请日：2017-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hoon BAEK ,  Sun-Young PARK ,  Sang-Kyu OH ,  Ha-Young KIM ,  Jung-Ho DO ,  Moo-Gyu BAE ,  Seung-Young LEE

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/11 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104

Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

公开(公告)号：US20200243523A1

公开(公告)日：2020-07-30

申请号：US16531327

申请日：2019-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Boong LEE ,  Jae-Ho PARK ,  Sang-Hoon BAEK ,  Ji-Su YU ,  Seung-Young LEE ,  Jong-Hoon JUNG

IPC: H01L27/092 ,  H01L29/06

Abstract: A semiconductor device includes first group active fins and a first diffusion prevention pattern. The first group active fins are spaced apart from each other in a second direction, and each of the first group active fins extends in a first direction different from the second direction on a first region of a substrate including the first region and a second region. The first diffusion prevention pattern extends on the first region of the substrate in the second direction through the first group active fins. The first group active fins include first and second active fins. The first diffusion prevention pattern extends through a central portion of the first active fin in the first direction to divide the first active fin, and extends through and contacts an end of the second active fin in the first direction.

公开(公告)号：US20180342505A1

公开(公告)日：2018-11-29

申请号：US16037581

申请日：2018-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hoon BAEK ,  Sun-Young PARK ,  Sang-Kyu OH ,  Ha-young KIM ,  Jung-Ho DO ,  Moo-Gyu BAE ,  Seung-Young LEE

IPC: H01L27/088 ,  H01L23/528 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/11

CPC classification number: H01L27/088 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1211

Abstract: A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.

公开(公告)号：US20200152627A1

公开(公告)日：2020-05-14

申请号：US16746071

申请日：2020-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hoon BAEK ,  Sun-Young PARK ,  Sang-Kyu OH ,  Ha-young KIM ,  Jung-Ho DO ,  Moo-Gyu BAE ,  Seung-Young LEE

IPC: H01L27/088 ,  H01L27/12 ,  H01L21/84 ,  H01L23/528 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/02

Abstract: A system on chip includes first to third nanowires extending in a second direction, first to third gate lines respectively surrounding the first to third nanowires, each of the first to third gate lines extending in a first direction across the second direction, a gate isolation region cutting the first to third gate lines and extending in the second direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact; and a second metal line electrically connected to the first gate contact.